A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2013, Pages 308-319

  Cook, Henry ^a   Moreto, Miquel ^a,b   Bird, Sarah ^a   Dao, Khanh ^a   Patterson, David A ^a   Asanovic, Krste ^a  

^a EECS Department   (United States)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE THROUGHPUT; CACHE PARTITIONING; COMPUTING WORKLOADS; DYNAMIC ALGORITHM; HARDWARE EVALUATIONS; PERFORMANCE DEGRADATION; PERFORMANCE GUARANTEES; STATIC APPROACH;

COMPUTER ARCHITECTURE; OPTIMIZATION; THROUGHPUT;

HARDWARE;

EID: 84881160871     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2485922.2485949     Document Type: Conference Paper

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