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Volumn , Issue , 2014, Pages

Variation aware cache partitioning for multithreaded programs

Author keywords

Multicores; Parallel Programs; Variation Aware Design; Variation Tol erance; Variations

Indexed keywords

COMPUTER AIDED DESIGN; MULTIPROCESSING PROGRAMS; MULTITASKING; PARALLEL ARCHITECTURES;

EID: 84903209395     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2593069.2593240     Document Type: Conference Paper
Times cited : (6)

References (19)
  • 1
    • 78650896343 scopus 로고    scopus 로고
    • Within-die variation-aware dynamic voltage frequency scaling with optimal core allocation and thread hopping for the 80-core teraops processor
    • S. Dighe et al. Within-die variation-aware dynamic voltage frequency scaling with optimal core allocation and thread hopping for the 80-core teraops processor. Trans. JSSC, 46(1), 2011.
    • (2011) Trans. JSSC , vol.46 , Issue.1
    • Dighe, S.1
  • 2
    • 77952656638 scopus 로고    scopus 로고
    • Variation-aware speed binning of multi-core processors
    • J. Sartori et al. Variation-aware speed binning of multi-core processors. In Proc. ISQED, pages 307-314, 2010.
    • (2010) Proc. ISQED , pp. 307-314
    • Sartori, J.1
  • 3
    • 1642371317 scopus 로고    scopus 로고
    • Dynamic partitioning of shared cache memory
    • April
    • G. E. Suh, L. Rudolph, and S. Devadas. Dynamic partitioning of shared cache memory. J. Supercomput., 28(1):7-26, April 2004.
    • (2004) J. Supercomput , vol.28 , Issue.1 , pp. 7-26
    • Suh, G.E.1    Rudolph, L.2    Devadas, S.3
  • 4
    • 78651391009 scopus 로고    scopus 로고
    • Quality of service shared cache management in chip multiprocessor architecture
    • F. Guo et al. Quality of service shared cache management in chip multiprocessor architecture. ACM TACO, 7(3):14:1-14:33, 2010.
    • (2010) ACM TACO , vol.7 , Issue.3 , pp. 1-14
    • Guo, F.1
  • 5
    • 38949186007 scopus 로고    scopus 로고
    • Varius: A model of process variation and resulting timing errors for microarchitects
    • S. R. Sarangi et al. VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects. IEEE Trans. Semiconductor Manufacturing,, 21(1):3-13, 2008.
    • (2008) IEEE Trans. Semiconductor Manufacturing , vol.21 , Issue.1 , pp. 3-13
    • Sarangi, S.R.1
  • 6
    • 34249813667 scopus 로고    scopus 로고
    • A performance counter architecture for computing accurate cpi components
    • S. Eyerman et al. A performance counter architecture for computing accurate CPI components. In Proc. ASPLOS, 2006.
    • (2006) Proc. ASPLOS
    • Eyerman, S.1
  • 8
    • 84867497756 scopus 로고    scopus 로고
    • Full-system simulation from embedded to high-performance systems
    • Springer US
    • J. Engblom et al. Full-system simulation from embedded to high-performance systems. In Processor and System-on-Chip Simulation, pages 25-45. Springer US, 2010.
    • (2010) Processor and System-on-Chip Simulation , pp. 25-45
    • Engblom, J.1
  • 9
    • 33748870886 scopus 로고    scopus 로고
    • Multifacet's general execution-driven multiprocessor simulator (gems) toolset
    • November
    • M. M. K. Martin et al. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput. Archit. News, 33(4):92-99, November 2005.
    • (2005) SIGARCH Comput. Archit. News , vol.33 , Issue.4 , pp. 92-99
    • Martin, M.M.K.1
  • 10
    • 70449689185 scopus 로고    scopus 로고
    • The parsec benchmark suite: Characterization and architectural implications
    • C. Bienia et al. The PARSEC benchmark suite: Characterization and architectural implications. In Proc. PACT, 2008.
    • (2008) Proc. PACT
    • Bienia, C.1
  • 11
    • 84900342836 scopus 로고    scopus 로고
    • Specomp: A new benchmark suite for measuring parallel computer performance
    • Springer-Verlag London, UK, UK
    • V. Aslot et al. SPEComp: A new benchmark suite for measuring parallel computer performance. In Proc. WOMPAT, pages 1-10, London, UK, UK, 2001. Springer-Verlag.
    • (2001) Proc. WOMPAT , pp. 1-10
    • Aslot, V.1
  • 12
    • 79955905510 scopus 로고    scopus 로고
    • Achieving uniform performance and maximizing throughput in the presence of heterogeneity
    • K. K. Rangan et al. Achieving uniform performance and maximizing throughput in the presence of heterogeneity. In Proc. HPCA, pages 3-14, 2011.
    • (2011) Proc. HPCA , pp. 3-14
    • Rangan, K.K.1
  • 13
    • 52649107085 scopus 로고    scopus 로고
    • Variation-aware application scheduling and power management for chip multiprocessors
    • R. Teodorescu et al. Variation-aware application scheduling and power management for chip multiprocessors. In Proc. ISCA, 2008.
    • (2008) Proc. ISCA
    • Teodorescu, R.1
  • 14
    • 70450245578 scopus 로고    scopus 로고
    • Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
    • A. Bhattacharjee et al. Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors. In Proc. ISCA, 2009.
    • (2009) Proc. ISCA
    • Bhattacharjee, A.1
  • 15
    • 64949121794 scopus 로고    scopus 로고
    • Variation-aware dynamic voltage/frequency scaling
    • S. Herbert et al. Variation-aware dynamic voltage/frequency scaling. In Proc. HPCA, pages 301-312, 2009.
    • (2009) Proc. HPCA , pp. 301-312
    • Herbert, S.1
  • 16
    • 10444238444 scopus 로고    scopus 로고
    • Fair cache sharing and partitioning in a chip multiprocessor architecture
    • S. Kim et al. Fair cache sharing and partitioning in a chip multiprocessor architecture. In Proc. PACT, pages 111-122, 2004.
    • (2004) Proc. PACT , pp. 111-122
    • Kim, S.1
  • 17
    • 84892536329 scopus 로고    scopus 로고
    • Imbalanced cache partitioning for balanced data-parallel programs
    • A. Pan et al. Imbalanced cache partitioning for balanced data-parallel programs. In Proc. Micro, pages 297-309, 2013.
    • (2013) Proc. Micro , pp. 297-309
    • Pan, A.1
  • 18
    • 77954012717 scopus 로고    scopus 로고
    • Intra-application cache partitioning
    • S.P. Muralidhara et al. Intra-application cache partitioning. In Proc. IPDPS, pages 1-12, 2010.
    • (2010) Proc. IPDPS , pp. 1-12
    • Muralidhara, S.P.1
  • 19
    • 80052675610 scopus 로고    scopus 로고
    • A helper thread based dynamic cache partitioning scheme for multithreaded applications
    • M. Kandemir et al. A helper thread based dynamic cache partitioning scheme for multithreaded applications. In Proc. DAC, pages 954-959, 2011.
    • (2011) Proc. DAC , pp. 954-959
    • Kandemir, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.