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Volumn , Issue , 2008, Pages 208-219

Adaptive insertion policies for managing shared caches

Author keywords

Cache Partitioning; Replacement; Set Dueling; Shared Cache

Indexed keywords

CACHE PARTITIONING; CACHE PERFORMANCE; CACHE STRUCTURES; CHIP MULTI PROCESSORS; MEMORY REQUIREMENTS; PERFORMANCE BENEFITS; REPLACEMENT; REPLACEMENT POLICIES; SET DUELING; SHARED CACHE; SINGLE CHIPS; STORAGE OVERHEADS; WORKING SETS;

EID: 63549149925     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1454115.1454145     Document Type: Conference Paper
Times cited : (242)

References (19)
  • 1
    • 34247150228 scopus 로고    scopus 로고
    • Intel core duo. White paper
    • Intel Corporation. Next leap in microprocessor architecture: Intel core duo. White paper, http://ces2006.akamai.com.edgesuite.net/yonahassets/CoreDuo- WhitePaper.pdf.
    • Next leap in microprocessor architecture
  • 2
    • 63549097778 scopus 로고    scopus 로고
    • H. Al-Zoubi, A. Milenkovic and M. Milenkovic. Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite. In ACMSE, 2004.
    • H. Al-Zoubi, A. Milenkovic and M. Milenkovic. Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite. In ACMSE, 2004.
  • 4
    • 8344246922 scopus 로고    scopus 로고
    • R. Iyer. CQoS: a framework for enabling QoS in shared caches of CMP platforms. In ICS-18,2004.
    • R. Iyer. CQoS: a framework for enabling QoS in shared caches of CMP platforms. In ICS-18,2004.
  • 6
    • 3042669130 scopus 로고    scopus 로고
    • R. Kalla, B. Sinharoy, and J. M. Tendler. IBM Power5 chip: A Dual-Core Multi-Threaded Processor. IEEE Micro, 24(2):40 {47, Mar. 2004.
    • R. Kalla, B. Sinharoy, and J. M. Tendler. IBM Power5 chip: A Dual-Core Multi-Threaded Processor. IEEE Micro, 24(2):40 {47, Mar. 2004.
  • 7
    • 10444238444 scopus 로고    scopus 로고
    • S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning in a chip multiprocessor architecture. In PACT-13, pages 111-122,2004.
    • S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning in a chip multiprocessor architecture. In PACT-13, pages 111-122,2004.
  • 8
    • 20344374162 scopus 로고    scopus 로고
    • P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-way multithreaded spare processor. IEEE Micro, 25(2):21 {29, March/April 2005.
    • P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-way multithreaded spare processor. IEEE Micro, 25(2):21 {29, March/April 2005.
  • 9
    • 31944440969 scopus 로고    scopus 로고
    • C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S.Wallace, V. J. Reddi, and K. Hazelwood. Pin: building customized program analysis tools with dynamic instrumentation. In PLDI, pages 190-200,2005.
    • C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S.Wallace, V. J. Reddi, and K. Hazelwood. Pin: building customized program analysis tools with dynamic instrumentation. In PLDI, pages 190-200,2005.
  • 10
    • 84962144701 scopus 로고    scopus 로고
    • Balancing throughput and fairness in smt processors
    • K. Luo, J. Gummaraju, and M. Franklin. Balancing throughput and fairness in smt processors. InlSPASS, pages 164-171, 2001.
    • (2001) InlSPASS , pp. 164-171
    • Luo, K.1    Gummaraju, J.2    Franklin, M.3
  • 11
    • 35348816719 scopus 로고    scopus 로고
    • K. J. Nesbit, J. Laudon, and J. E. Smith. Virtual private caches. In ISCA-34, pages 57-68,2007.
    • K. J. Nesbit, J. Laudon, and J. E. Smith. Virtual private caches. In ISCA-34, pages 57-68,2007.
  • 13
    • 34548042910 scopus 로고    scopus 로고
    • M. K. Qureshi and Y. Patt. Utility Based Cache Partitioning: A Low Overhead High-Performance Runtime Mechanism to Partition Shared Caches. In MICRO-39,2006.
    • M. K. Qureshi and Y. Patt. Utility Based Cache Partitioning: A Low Overhead High-Performance Runtime Mechanism to Partition Shared Caches. In MICRO-39,2006.
  • 15
    • 34547655822 scopus 로고    scopus 로고
    • S. Srinath, O.Mutlu, H. Kim, and Y. N. Patt. Feedback directed prefetching: Improving the performance and bandwidthefficiency of hardware prefetchers. In HPCA-13,2007.
    • S. Srinath, O.Mutlu, H. Kim, and Y. N. Patt. Feedback directed prefetching: Improving the performance and bandwidthefficiency of hardware prefetchers. In HPCA-13,2007.
  • 16
    • 0034443570 scopus 로고    scopus 로고
    • Symbiotic Jobscheduling for a Simultaneous Multithreading Processor
    • A. Snavely and D. Tullsen. "Symbiotic Jobscheduling for a Simultaneous Multithreading Processor". In ASPLOS IX, 2000.
    • (2000) ASPLOS , vol.9
    • Snavely, A.1    Tullsen, D.2


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