-
1
-
-
0035054940
-
A 4Gb DDR SDRAM with Gain-Controlled Pre-Sensing and Reference Bitline Calibration Schemes in the Twisted Open Bitline Architecture
-
February
-
H. Yoon, J. Y. Sim, H. S. Lee, K. N. Lim, J. Y. Lee, N. J. Kim, K. Y. Kim, S. M. Byun, W. S. Yang, C. H. Choi, H. S. Jeong, J. H. Yoo, D. I. Seo, K. Kim, B. I. Ryu, and C. G. Hwang, "A 4Gb DDR SDRAM with Gain-Controlled Pre-Sensing and Reference Bitline Calibration Schemes in the Twisted Open Bitline Architecture," ISSCC Digest of Technical Papers, February 2001, pp. 378-379.
-
(2001)
ISSCC Digest of Technical Papers
, pp. 378-379
-
-
Yoon, H.1
Sim, J.Y.2
Lee, H.S.3
Lim, K.N.4
Lee, J.Y.5
Kim, N.J.6
Kim, K.Y.7
Byun, S.M.8
Yang, W.S.9
Choi, C.H.10
Jeong, H.S.11
Yoo, J.H.12
Seo, D.I.13
Kim, K.14
Ryu, B.I.15
Hwang, C.G.16
-
2
-
-
0036051766
-
Highly Manufacturable 32Mb ULP-SRAM Technology by Using Dual Gate Process for 1.5V Vcc Operation
-
June
-
D. H. Kim, S. J. Kim, B. J. Hwang, S. H. Seo, J. H. Choi, H. S. Lee, W. S. Yang, M. S. Kim, K. H. Kwak, J. Y. Lee, J. Y. Joo, J. H. Kim, K. Koh, S. H. Park, and J. I. Hong, "Highly Manufacturable 32Mb ULP-SRAM Technology by Using Dual Gate Process for 1.5V Vcc Operation," Symposium on VLSI Technology, Digest of Technical Papers, June 2002, pp. 118-119.
-
(2002)
Symposium on VLSI Technology, Digest of Technical Papers
, pp. 118-119
-
-
Kim, D.H.1
Kim, S.J.2
Hwang, B.J.3
Seo, S.H.4
Choi, J.H.5
Lee, H.S.6
Yang, W.S.7
Kim, M.S.8
Kwak, K.H.9
Lee, J.Y.10
Joo, J.Y.11
Kim, J.H.12
Koh, K.13
Park, S.H.14
Hong, J.I.15
-
3
-
-
0037630808
-
A 1.2V 1.5Gb/s 72Mb DDR3 SRAM
-
February
-
U.-R. Cho, T.-H. Kim, Y.-J. Yoon, J.-C. Lee, D.-G. Bae, N.-S. Kim, K.-Y. Kim, Y.-J. Son, J.-S. Yang, K.-I. Sohn, S.-T. Kim, I.-Y. Lee, K.-J. Lee, T.-G. Kang, S.-C. Kim, K.-S. Ahnb, and H.-G. Byun, "A 1.2V 1.5Gb/s 72Mb DDR3 SRAM," ISSCC Digest of Technical Papers, February 2003, pp. 300-301.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 300-301
-
-
Cho, U.-R.1
Kim, T.-H.2
Yoon, Y.-J.3
Lee, J.-C.4
Bae, D.-G.5
Kim, N.-S.6
Kim, K.-Y.7
Son, Y.-J.8
Yang, J.-S.9
Sohn, K.-I.10
Kim, S.-T.11
Lee, I.-Y.12
Lee, K.-J.13
Kang, T.-G.14
Kim, S.-C.15
Ahnb, K.-S.16
Byun, H.-G.17
-
5
-
-
0036116460
-
A 300MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write
-
February
-
J. Barth, D. Anand, J. Dreibelbis, and E. Nelson, "A 300MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write," ISSCC Digest of Technical Papers, February 2002, pp. 156-157.
-
(2002)
ISSCC Digest of Technical Papers
, pp. 156-157
-
-
Barth, J.1
Anand, D.2
Dreibelbis, J.3
Nelson, E.4
-
6
-
-
0036116198
-
The On-Chip 3MB Subarray Based 3rd Level Cache on an Itanium Microprocessor
-
February
-
D. Weiss, J. J. Wuu, and V. Chin, "The On-Chip 3MB Subarray Based 3rd Level Cache on an Itanium Microprocessor," ISSCC Digest of Technical Papers, February 2002, pp. 112-113.
-
(2002)
ISSCC Digest of Technical Papers
, pp. 112-113
-
-
Weiss, D.1
Wuu, J.J.2
Chin, V.3
-
7
-
-
0034453480
-
Reviews and Prospects of High-Density RAM Technology
-
October, Sinaia (Romania)
-
K. Itoh, T. Watanabe, S. Kimura, and T. Sakata, "Reviews and Prospects of High-Density RAM Technology," Proceedings of CAS 2000, October 2000, Sinaia (Romania), pp. 13-22.
-
(2000)
Proceedings of CAS 2000
, pp. 13-22
-
-
Itoh, K.1
Watanabe, T.2
Kimura, S.3
Sakata, T.4
-
10
-
-
0024927760
-
A 1.5V DRAM for Battery-Based Applications
-
February
-
M. Aoki, J. Etoh, K. Itoh, S. Kimura, and Y. Kawamoto, "A 1.5V DRAM for Battery-Based Applications," ISSCC Digest of Technical Papers, February 1989, pp. 238-239.
-
(1989)
ISSCC Digest of Technical Papers
, pp. 238-239
-
-
Aoki, M.1
Etoh, J.2
Itoh, K.3
Kimura, S.4
Kawamoto, Y.5
-
11
-
-
0025537328
-
A 1.5-V Circuit Technology for 64Mb DRAMs
-
June
-
Y. Nakagome, Y. Kawamoto, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda, and K. Itoh, "A 1.5-V Circuit Technology for 64Mb DRAMs," Symposium on VLSI Circuits, Digest of Technical Papers, June 1990, pp. 17-18.
-
(1990)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 17-18
-
-
Nakagome, Y.1
Kawamoto, Y.2
Tanaka, H.3
Takeuchi, K.4
Kume, E.5
Watanabe, Y.6
Kaga, T.7
Murai, F.8
Izawa, R.9
Hisamoto, D.10
Kisu, T.11
Nishida, T.12
Takeda, E.13
Itoh, K.14
-
12
-
-
0347976385
-
-
U.S. Patent 5,297,097, March
-
J. Etoh, K. Itoh, Y. Kawajiri, Y. Nakagome, E. Kume, and H. Tanaka, "Large Scale Integrated Circuit for Low Voltage Operation," U.S. Patent 5,297,097, March 1994.
-
(1994)
Large Scale Integrated Circuit for Low Voltage Operation
-
-
Etoh, J.1
Itoh, K.2
Kawajiri, Y.3
Nakagome, Y.4
Kume, E.5
Tanaka, H.6
-
13
-
-
0347346114
-
Sub-1-V Swing Bus Architecture for Future Low-Power ULSIs
-
June
-
Y. Nakagome, K. Itoh, M. Isoda, K. Takeuchi, and M. Aoki, "Sub-1-V Swing Bus Architecture for Future Low-Power ULSIs," Symposium on VLSI Circuits, Digest of Technical Papers, June 1992, pp. 82-83.
-
(1992)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 82-83
-
-
Nakagome, Y.1
Itoh, K.2
Isoda, M.3
Takeuchi, K.4
Aoki, M.5
-
14
-
-
0027700917
-
Subthreshold Current Reduction for Decoded-Driver by Self-Reverse Biasing
-
November
-
T. Kawahara, M. Horiguchi, Y. Kawajiri, G. Kitsukawa, T. Kure, and M. Aoki, "Subthreshold Current Reduction for Decoded-Driver by Self-Reverse Biasing," IEEE J. Solid-State Circuits 28, No. 11, 1136-1144 (November 1993).
-
(1993)
IEEE J. Solid-state Circuits
, vol.28
, Issue.11
, pp. 1136-1144
-
-
Kawahara, T.1
Horiguchi, M.2
Kawajiri, Y.3
Kitsukawa, G.4
Kure, T.5
Aoki, M.6
-
15
-
-
0027698768
-
Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSI's
-
November
-
M. Horiguchi, T. Sakata, and K. Itoh, "Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSI's," IEEE J. Solid-State Circuits 28, No. 11, 1131-1135 (November 1993).
-
(1993)
IEEE J. Solid-state Circuits
, vol.28
, Issue.11
, pp. 1131-1135
-
-
Horiguchi, M.1
Sakata, T.2
Itoh, K.3
-
16
-
-
0028416570
-
Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory
-
April
-
D. Takashima, S. Watanabe, H. Nakano, Y. Oowaki, K. Ohuchi, and H. Tango, "Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory," IEEE J. Solid-State Circuits 29, No. 4, 441-447 (April 1994).
-
(1994)
IEEE J. Solid-state Circuits
, vol.29
, Issue.4
, pp. 441-447
-
-
Takashima, D.1
Watanabe, S.2
Nakano, H.3
Oowaki, Y.4
Ohuchi, K.5
Tango, H.6
-
17
-
-
0029359285
-
1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS
-
August
-
S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS," IEEE J. Solid-State Circuits 30, No. 8, 847-854 (August 1995).
-
(1995)
IEEE J. Solid-state Circuits
, vol.30
, Issue.8
, pp. 847-854
-
-
Mutoh, S.1
Douseki, T.2
Matsuya, Y.3
Aoki, T.4
Shigematsu, S.5
Yamada, J.6
-
18
-
-
0028465148
-
Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAM's
-
July
-
T. Sakata, K. Itoh, M. Horiguchi, and M. Aoki, "Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAM's," IEEE J. Solid-State Circuits 29, No. 7, 761-769 (July 1994).
-
(1994)
IEEE J. Solid-state Circuits
, vol.29
, Issue.7
, pp. 761-769
-
-
Sakata, T.1
Itoh, K.2
Horiguchi, M.3
Aoki, M.4
-
19
-
-
0029288557
-
Trends in Low-Power RAM Circuit Technologies
-
April
-
K. Itoh, K. Sasaki, and Y. Nakagome, "Trends in Low-Power RAM Circuit Technologies," Proc. IEEE 83, No. 4, 524-543 (April 1995).
-
(1995)
Proc. IEEE
, vol.83
, Issue.4
, pp. 524-543
-
-
Itoh, K.1
Sasaki, K.2
Nakagome, Y.3
-
20
-
-
48349095517
-
Current and Future Trend on Cosmic-Ray-Neutron Induced Single Event Upset at the Ground Down to 0.1-Micron-Devices
-
May, Uppsala, Sweden
-
E. Ibe, "Current and Future Trend on Cosmic-Ray-Neutron Induced Single Event Upset at the Ground Down to 0.1-Micron-Devices," presented at the Svedberg Laboratory Workshop on Applied Physics, May 2001, Uppsala, Sweden.
-
(2001)
Svedberg Laboratory Workshop on Applied Physics
-
-
Ibe, E.1
-
21
-
-
0031122158
-
CMOS Scaling into the Nanometer Regime
-
April
-
Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S.-H. Lo, G. A. Sai-Halasz, R. G. Viswanathan, H.-J. C. Wann, S. J. Wind, and H.-S. Wong, "CMOS Scaling into the Nanometer Regime," Proc. IEEE 85, No. 4, 486-504 (April 1997).
-
(1997)
Proc. IEEE
, vol.85
, Issue.4
, pp. 486-504
-
-
Taur, Y.1
Buchanan, D.A.2
Chen, W.3
Frank, D.J.4
Ismail, K.E.5
Lo, S.-H.6
Sai-Halasz, G.A.7
Viswanathan, R.G.8
Wann, H.-J.C.9
Wind, S.J.10
Wong, H.-S.11
-
22
-
-
0036772398
-
Low-Voltage DRAM Sensing Scheme with Offset-Cancellation Sense Amplifier
-
October
-
S. Hong, S. Kim, J.-K. Wee, and S. Lee, "Low-Voltage DRAM Sensing Scheme with Offset-Cancellation Sense Amplifier," IEEE J. Solid-State Circuits 37, No. 10, 1356-1360 (October 2002).
-
(2002)
IEEE J. Solid-state Circuits
, vol.37
, Issue.10
, pp. 1356-1360
-
-
Hong, S.1
Kim, S.2
Wee, J.-K.3
Lee, S.4
-
23
-
-
0038306336
-
A 1.0V 256Mb SDRAM with Offset-Compensated Direct Sensing and Charge-Recycled Precharge Scheme
-
February
-
J. Y. Sim, K. W. Kwon, J. H. Choi, S. H. Lee, D. M. Kim, H. R. Hwang, K. C. Chun, Y. H. Seo, H. S. Hwang, D. I. Seo, and S. I. Cho, "A 1.0V 256Mb SDRAM with Offset-Compensated Direct Sensing and Charge-Recycled Precharge Scheme," ISSCC Digest of Technical Papers, February 2003, pp. 310-311.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 310-311
-
-
Sim, J.Y.1
Kwon, K.W.2
Choi, J.H.3
Lee, S.H.4
Kim, D.M.5
Hwang, H.R.6
Chun, K.C.7
Seo, Y.H.8
Hwang, H.S.9
Seo, D.I.10
Cho, S.I.11
-
24
-
-
0025505721
-
A 50-ns 16-Mb DRAM with a 10-ns Data Rate and On-Chip ECC
-
October
-
H. L. Kalter, C. H. Stapper, J. E. Barth Jr., J. DiLorenzo, C. E. Drake, J. A. Fifield, G. A. Kelley, Jr., S. C. Lewis, W. B. van der Hoeven, and J. A. Yankosky, "A 50-ns 16-Mb DRAM with a 10-ns Data Rate and On-Chip ECC, " IEEE J. Solid-State Circuits 25, No. 5, 1118-1128 (October 1990).
-
(1990)
IEEE J. Solid-state Circuits
, vol.25
, Issue.5
, pp. 1118-1128
-
-
Kalter, H.L.1
Stapper, C.H.2
Barth Jr., J.E.3
Dilorenzo, J.4
Drake, C.E.5
Fifield, J.A.6
Kelley Jr., G.A.7
Lewis, S.C.8
Van der Hoeven, W.B.9
Yankosky, J.A.10
-
25
-
-
0242425984
-
16.7fA/ Cell Tunnel-Leakage-Suppressed 16-Mbit SRAM Based on Electric-Field-Relaxed Scheme and Alternate ECC for Handling Cosmic-Ray-Induced Multi-Errors
-
February
-
K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi, "16.7fA/ Cell Tunnel-Leakage-Suppressed 16-Mbit SRAM Based on Electric-Field-Relaxed Scheme and Alternate ECC for Handling Cosmic-Ray-Induced Multi-Errors," ISSCC Digest of Technical Papers, February 2003, pp. 302-303.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 302-303
-
-
Osada, K.1
Saitoh, Y.2
Ibe, E.3
Ishibashi, K.4
-
26
-
-
84928236510
-
Reviews and Prospects of Low-Power Memory Circuits
-
A. Chandrakasan and R. Brodersen, Eds., Wiley-IEEE Press, Hoboken, NJ
-
K. Itoh, "Reviews and Prospects of Low-Power Memory Circuits" (invited), Low-Power CMOS Design, A. Chandrakasan and R. Brodersen, Eds., Wiley-IEEE Press, Hoboken, NJ, 1998, pp. 313-317.
-
(1998)
Low-power CMOS Design
, pp. 313-317
-
-
Itoh, K.1
-
28
-
-
0034429685
-
IGHz Fully Pipelined 3.7ns Address Access Time 8k × 1024 Embedded DRAM Macro
-
February
-
O. Takahashi, S. Dhong, M. Ohkubo, S. Onishi, R. Dennard, R. Hannon, S. Crowder, S. Iyer, M. Wordeman, B. Davari, W. B. Weinberger, and N. Aoki, "IGHz Fully Pipelined 3.7ns Address Access Time 8k × 1024 Embedded DRAM Macro," ISSCC Digest of Technical Papers, February 2000, pp. 396-397.
-
(2000)
ISSCC Digest of Technical Papers
, pp. 396-397
-
-
Takahashi, O.1
Dhong, S.2
Ohkubo, M.3
Onishi, S.4
Dennard, R.5
Hannon, R.6
Crowder, S.7
Iyer, S.8
Wordeman, M.9
Davari, B.10
Weinberger, W.B.11
Aoki, N.12
-
30
-
-
0036508274
-
Power-Constrained CMOS Scaling Limits
-
March
-
D. J. Frank, "Power-Constrained CMOS Scaling Limits," IBM J. Res. & Dev. 46, No. 2/3, 235-244 (March 2002).
-
(2002)
IBM J. Res. & Dev.
, vol.46
, Issue.2-3
, pp. 235-244
-
-
Frank, D.J.1
-
32
-
-
0028013943
-
Limitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation
-
May
-
S. Wei Sun and P. G. Y. Tsui, "Limitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation," Proceedings of the CICC, May 1994, pp. 267-270.
-
(1994)
Proceedings of the CICC
, pp. 267-270
-
-
Sun, S.W.1
Tsui, P.G.Y.2
-
33
-
-
0033683109
-
2 Trench-Sidewall Vertical Device Cell for 4 Gb/16 Gb DRAM
-
June
-
2 Trench-Sidewall Vertical Device Cell for 4 Gb/16 Gb DRAM," Symposium on VLSI Technology, Digest of Technical Papers, June 2000, pp. 80-81.
-
(2000)
Symposium on VLSI Technology, Digest of Technical Papers
, pp. 80-81
-
-
Radens, C.J.1
Gruening, U.2
Mandelman, J.A.3
Seitz, M.4
Dyer, T.5
Lea, D.6
Casarotto, D.7
Clevenger, L.8
Nesbit, L.9
Malik, R.10
Halle, S.11
Kudelka, S.12
Tews, H.13
Divakaruni, R.14
Sim, J.15
Strong, A.16
Tibbel, D.17
Arnold, N.18
Bukofsky, S.19
Preuninger, J.20
Kunkel, G.21
Bronner, G.22
more..
-
35
-
-
0035054826
-
2 Open-Bit-Line Cell Distributed Over-Driven Sensing and Stacked-Flash Fuse
-
February
-
2 Open-Bit-Line Cell Distributed Over-Driven Sensing and Stacked-Flash Fuse," ISSCC Digest of Technical Papers, February 2001, pp. 380-381.
-
(2001)
ISSCC Digest of Technical Papers
, pp. 380-381
-
-
Takahashi, T.1
Sekiguchi, T.2
Takemura, R.3
Narui, S.4
Fujisawa, H.5
Miyatake, S.6
Morino, M.7
Arai, K.8
Yamada, S.9
Shukuri, S.10
Nakamura, M.11
Tadaki, Y.12
Kajigaya, K.13
Kimura, K.14
Itoh, K.15
-
36
-
-
0036539318
-
A Low-Impedance Open-Bitline Array for Multigigabit DRAM
-
April
-
T. Sekiguchi, K. Itoh, T. Takahashi, M. Sugaya, H. Fujisawa, M. Nakamura, K. Kajigaya, and K. Kimura, "A Low-Impedance Open-Bitline Array for Multigigabit DRAM," IEEE J. Solid-State Circuits 37, No. 4, 487-498 (April 2002).
-
(2002)
IEEE J. Solid-state Circuits
, vol.37
, Issue.4
, pp. 487-498
-
-
Sekiguchi, T.1
Itoh, K.2
Takahashi, T.3
Sugaya, M.4
Fujisawa, H.5
Nakamura, M.6
Kajigaya, K.7
Kimura, K.8
-
38
-
-
0033681233
-
The Ideal SoC Memory: 1T-SRAM
-
September
-
W. Leung, F.-C. Hsu, and M.-E. Jones, "The Ideal SoC Memory: 1T-SRAM," Proceedings of the 13th Annual IEEE International ASIC/SOC Conference, September 2000, pp. 32-36.
-
(2000)
Proceedings of the 13th Annual IEEE International ASIC/SOC Conference
, pp. 32-36
-
-
Leung, W.1
Hsu, F.-C.2
Jones, M.-E.3
-
39
-
-
0346085073
-
1T-Cell DRAM with MOS Storage Capacitors in a 130nm Logic Technology for High Density Microprocessors Caches
-
September
-
D. Somasekhar, S. Lu, B. Bloechel, K. Lai, S. Borkar, and V. De Planar, "1T-Cell DRAM with MOS Storage Capacitors in a 130nm Logic Technology for High Density Microprocessors Caches," Proceedings of the ESSCIRC, September 2002, pp. 127-130.
-
(2002)
Proceedings of the ESSCIRC
, pp. 127-130
-
-
Somasekhar, D.1
Lu, S.2
Bloechel, B.3
Lai, K.4
Borkar, S.5
De Planar, V.6
-
40
-
-
0030084869
-
Implementing Application Specific Memory
-
February
-
R. C. Foss, "Implementing Application Specific Memory," ISSCC Digest of Technical Papers, February 1996, pp. 260-261.
-
(1996)
ISSCC Digest of Technical Papers
, pp. 260-261
-
-
Foss, R.C.1
-
41
-
-
0034429810
-
Phase-State Low Electron-Number Drive Random Access Memory (PLEDM)
-
February
-
K. Nakazato, K. Itoh, H. Ahmed, H. Mizuta, T. Kisu, M. Kato, and T. Sakata, "Phase-State Low Electron-Number Drive Random Access Memory (PLEDM)," ISSCC Digest of Technical Papers, February 2000, pp. 132-133.
-
(2000)
ISSCC Digest of Technical Papers
, pp. 132-133
-
-
Nakazato, K.1
Itoh, K.2
Ahmed, H.3
Mizuta, H.4
Kisu, T.5
Kato, M.6
Sakata, T.7
-
42
-
-
0032277570
-
2/ Loadless CMOS Four-Transistor SRAM Cell in a 0.18-μm Logic Technology
-
December
-
2/ Loadless CMOS Four-Transistor SRAM Cell in a 0.18-μm Logic Technology," IEDM Tech. Digest, pp. 643-646 (December 1998).
-
(1998)
IEDM Tech. Digest
, pp. 643-646
-
-
Noda, K.1
Matsui, K.2
Imai, K.3
Inoue, K.4
Tokashiki, K.5
Kawamoto, H.6
Yoshida, K.7
Takeda, K.8
Nakamura, N.9
Kimura, T.10
Toyoshima, H.11
Koishikawa, Y.12
Maruyama, S.13
Saitoh, T.14
Tanigawa, T.15
-
43
-
-
0036611472
-
Leakage Scaling in Deep Submicron CMOS for SoC
-
June
-
Y. Lin, C. Wu, C. Chang, R. Yang, W. Chen, J. Liaw, and C. Diaz, "Leakage Scaling in Deep Submicron CMOS for SoC," IEEE Trans. Electron Devices 49, No. 6, 1034-1041 (June 2002).
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.6
, pp. 1034-1041
-
-
Lin, Y.1
Wu, C.2
Chang, C.3
Yang, R.4
Chen, W.5
Liaw, J.6
Diaz, C.7
-
44
-
-
0242611669
-
A 6GHz, 16Kbytes L1 Cache in a 100nm Dual-V/ Sub-T/ Technology Using a Bitline Leakage Reduction (BLR) Technique
-
June
-
Y. Ye, M. Khellah, D. Somasekhar, A. Farhang, and V. De, "A 6GHz, 16Kbytes L1 Cache in a 100nm Dual-V/ Sub-T/ Technology Using a Bitline Leakage Reduction (BLR) Technique," Symposium on VLSI Circuits, Digest of Technical Papers, June 2002, pp. 50-51.
-
(2002)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 50-51
-
-
Ye, Y.1
Khellah, M.2
Somasekhar, D.3
Farhang, A.4
De, V.5
-
45
-
-
0028419741
-
A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers
-
April
-
K. Ishibashi, K. Komiyaji, S. Morita, T. Aoto, S. Ikeda, K. Asayama, A. Koike, T. Yamanaka, N. Hashimoto, H. Iida, F. Kojima, K. Motohashi, and K. Sasaki, "A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers," IEEE J. Solid-State Circuits 29, No. 4, 411-418 (April 1994).
-
(1994)
IEEE J. Solid-state Circuits
, vol.29
, Issue.4
, pp. 411-418
-
-
Ishibashi, K.1
Komiyaji, K.2
Morita, S.3
Aoto, T.4
Ikeda, S.5
Asayama, K.6
Koike, A.7
Yamanaka, T.8
Hashimoto, N.9
Iida, H.10
Kojima, F.11
Motohashi, K.12
Sasaki, K.13
-
46
-
-
17144462799
-
A 500-MHz Pipelined Burst SRAM with Improved SER Immunity
-
November
-
H. Sato, T. Wada, S. Ohbayashi, K. Kozaru, Y. Okamoto, Y. Higashide, T. Shimizu, Y. Maki, R. Morimoto, H. Otoi, T. Koga, H. Honda, M. Taniguchi, Y. Arita, and T. Shiomi, "A 500-MHz Pipelined Burst SRAM with Improved SER Immunity," IEEE J. Solid-State Circuits 34, No. 11, 1571-1579 (November 1999).
-
(1999)
IEEE J. Solid-state Circuits
, vol.34
, Issue.11
, pp. 1571-1579
-
-
Sato, H.1
Wada, T.2
Ohbayashi, S.3
Kozaru, K.4
Okamoto, Y.5
Higashide, Y.6
Shimizu, T.7
Maki, Y.8
Morimoto, R.9
Otoi, H.10
Koga, T.11
Honda, H.12
Taniguchi, M.13
Arita, Y.14
Shiomi, T.15
-
47
-
-
0029702076
-
t, Boosted Storage Node and Dynamic Load
-
June
-
t, Boosted Storage Node and Dynamic Load," Symposium on VLSI Circuits, Digest of Technical Papers, June 1996, pp. 132-133.
-
(1996)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 132-133
-
-
Itoh, K.1
Fridi, A.R.2
Bellaouar, A.3
Elmasry, M.I.4
-
48
-
-
0242611631
-
0.4-V Logic Library Friendly SRAM Array Using Rectangular-Diffusion Cell and Delta-Boosted-Array Voltage Scheme
-
June
-
M. Yamaoka, K. Osada, and K. Ishibashi, "0.4-V Logic Library Friendly SRAM Array Using Rectangular-Diffusion Cell and Delta-Boosted-Array Voltage Scheme," Symposium on VLSI Circuits, Digest of Technical Papers, June 2002, pp. 170-173.
-
(2002)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 170-173
-
-
Yamaoka, M.1
Osada, K.2
Ishibashi, K.3
-
49
-
-
0034867611
-
Scaling of Stack Effect and its Application for Leakage Reduction
-
August
-
S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, "Scaling of Stack Effect and its Application for Leakage Reduction," Proceedings of the ISLPED, August 2001, pp. 195-199.
-
(2001)
Proceedings of the ISLPED
, pp. 195-199
-
-
Narendra, S.1
Borkar, S.2
De, V.3
Antoniadis, D.4
Chandrakasan, A.5
-
50
-
-
0029253931
-
50% Active-Power Saving Without Speed Degradation Using Standby Power Reduction (SPR) Circuit
-
February
-
K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai, "50% Active-Power Saving Without Speed Degradation Using Standby Power Reduction (SPR) Circuit," ISSCC Digest of Technical Papers, February 1995. pp. 318-319.
-
(1995)
ISSCC Digest of Technical Papers
, pp. 318-319
-
-
Seta, K.1
Hara, H.2
Kuroda, T.3
Kakumu, M.4
Sakurai, T.5
-
51
-
-
0031641123
-
A Novel Powering-Down Scheme for Low Vt CMOS Circuits
-
June
-
K. Kumagai, H. Iwaki, H. Yoshida, H. Suzuki, T. Yamada, and S. Kurosawa, "A Novel Powering-Down Scheme for Low Vt CMOS Circuits," Symposium on VLSI Circuits, Digest of Technical Papers, June 1998, pp. 44-45.
-
(1998)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 44-45
-
-
Kumagai, K.1
Iwaki, H.2
Yoshida, H.3
Suzuki, H.4
Yamada, T.5
Kurosawa, S.6
-
52
-
-
0030081933
-
Elastic-Vt CMOS Circuits for Multiple On-Chip Power Control
-
February
-
M. Mizuno, K. Furuta, S. Narita, H. Abiko, I. Sakai, and M. Yamashina, "Elastic-Vt CMOS Circuits for Multiple On-Chip Power Control," ISSCC Digest of Technical Papers, February 1996, pp. 300-301.
-
(1996)
ISSCC Digest of Technical Papers
, pp. 300-301
-
-
Mizuno, M.1
Furuta, K.2
Narita, S.3
Abiko, H.4
Sakai, I.5
Yamashina, M.6
-
53
-
-
0032202541
-
eff CMOS Technology with Copper Interconnects
-
November
-
eff CMOS Technology with Copper Interconnects," IEEE J. Solid-State Circuits 33, No. 11, 1609-1616 (November 1998).
-
(1998)
IEEE J. Solid-state Circuits
, vol.33
, Issue.11
, pp. 1609-1616
-
-
Akrout, C.1
Bialas, J.2
Canada, M.3
Cawthron, D.4
Corr, J.5
Davari, B.6
Floyd, R.7
Geissler, S.8
Goldblatt, R.9
Houle, R.10
Kartschoke, P.11
Kramer, D.12
McCormick, P.13
Rohrer, N.14
Salem, G.15
Schulz, R.16
Su, L.17
Whitney, L.18
-
55
-
-
0347346056
-
A Single 5V 64K Dynamic RAM
-
February
-
K. Itoh, R. Hori, H. Masuda, Y. Kawajiri, H. Kawamoto, and H. Katto, "A Single 5V 64K Dynamic RAM," ISSCC Digest of Technical Papers, February 1980, pp. 228-229.
-
(1980)
ISSCC Digest of Technical Papers
, pp. 228-229
-
-
Itoh, K.1
Hori, R.2
Masuda, H.3
Kawajiri, Y.4
Kawamoto, H.5
Katto, H.6
-
56
-
-
0031621632
-
A Low-Power SRAM Using Improved Charge Transfer Sense Amplifiers and a Dual-Vth CMOS Circuit Scheme
-
June
-
I. Fukushi, R. Sasagawa, M. Hamaminato, T. Izawa, and S. Kawashima, "A Low-Power SRAM Using Improved Charge Transfer Sense Amplifiers and a Dual-Vth CMOS Circuit Scheme," Symposium on VLSI Circuits, Digest of Technical Papers, June 1998, pp. 142-145.
-
(1998)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 142-145
-
-
Fukushi, I.1
Sasagawa, R.2
Hamaminato, M.3
Izawa, T.4
Kawashima, S.5
-
57
-
-
0031678266
-
A 256Mb SDRAM with Subthreshold Leakage Current Suppression
-
February
-
M. Hasegawa, M. Nakamura, S. Narui, S. Ohkuma, Y. Kawase, H. Endoh, S. Miyatake, T. Akiba, K. Kawakita, M. Yoshida, S. Yamada, T. Sekiguchi, I. Asano, Y. Tadaki, R. Nagai, S. Miyaoka, K. Kajigaya, M. Horiguchi, and Y. Nakagome, "A 256Mb SDRAM with Subthreshold Leakage Current Suppression," ISSCC Digest of Technical Papers, February 1998, pp. 80-81.
-
(1998)
ISSCC Digest of Technical Papers
, pp. 80-81
-
-
Hasegawa, M.1
Nakamura, M.2
Narui, S.3
Ohkuma, S.4
Kawase, Y.5
Endoh, H.6
Miyatake, S.7
Akiba, T.8
Kawakita, K.9
Yoshida, M.10
Yamada, S.11
Sekiguchi, T.12
Asano, I.13
Tadaki, Y.14
Nagai, R.15
Miyaoka, S.16
Kajigaya, K.17
Horiguchi, M.18
Nakagome, Y.19
-
58
-
-
0031635212
-
A New Technique for Standby Leakage Reduction in High-Performance Circuits
-
June
-
Y. Ye, S. Borkar, and V. De, "A New Technique for Standby Leakage Reduction in High-Performance Circuits," Symposium on VLSI Circuits, Digest of Technical Papers, June 1998, pp. 40-41.
-
(1998)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 40-41
-
-
Ye, Y.1
Borkar, S.2
De, V.3
-
59
-
-
0030712582
-
A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits
-
May
-
J. P. Halter and F. N. Najm, "A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits," Proceedings of the CICC, May 1997, pp. 475-478.
-
(1997)
Proceedings of the CICC
, pp. 475-478
-
-
Halter, J.P.1
Najm, F.N.2
-
60
-
-
0034293891
-
A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current
-
October
-
H. Kawaguchi, K. Nose, and T. Sakurai, "A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current, " IEEE J. Solid-State Circuits 35, No. 10, 1498-1501 (October 2000).
-
(2000)
IEEE J. Solid-state Circuits
, vol.35
, Issue.10
, pp. 1498-1501
-
-
Kawaguchi, H.1
Nose, K.2
Sakurai, T.3
-
61
-
-
0029406986
-
Low Voltage Circuit Design Techniques for Battery-Operated and/or Giga-Scale DRAM's
-
November
-
T. Yamagata, S. Tomishima, M. Tsukude, T. Tsuruda, Y. Hashizume, and K. Arimoto, "Low Voltage Circuit Design Techniques for Battery-Operated and/ or Giga-Scale DRAM's," IEEE J. Solid-State Circuits 30, No. 11, 1183-1188 (November 1995).
-
(1995)
IEEE J. Solid-state Circuits
, vol.30
, Issue.11
, pp. 1183-1188
-
-
Yamagata, T.1
Tomishima, S.2
Tsukude, M.3
Tsuruda, T.4
Hashizume, Y.5
Arimoto, K.6
-
62
-
-
0030086605
-
2, 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme
-
February
-
2, 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme," ISSCC Digest of Technical Papers, February 1996, pp. 166-167.
-
(1996)
ISSCC Digest of Technical Papers
, pp. 166-167
-
-
Kuroda, T.1
Fujita, T.2
Mita, S.3
Nagamatu, T.4
Yoshioka, S.5
Sano, F.6
Norishima, M.7
Murota, M.8
Kako, M.9
Kinugawa, M.10
Kakumu, M.11
Sakurai, T.12
-
63
-
-
0033221245
-
A 18-μA Standby Current 1.8-V 200-MHz Microprocessor with Self-Substrate-Biased Data-Retention Mode
-
November
-
H. Mizuno, K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S. Ikeda, and K. Uchiyama, "A 18-μA Standby Current 1.8-V 200-MHz Microprocessor with Self-Substrate-Biased Data-Retention Mode," IEEE J. Solid-State Circuits 34, No. 11, 1492-1500 (November 1999).
-
(1999)
IEEE J. Solid-state Circuits
, vol.34
, Issue.11
, pp. 1492-1500
-
-
Mizuno, H.1
Ishibashi, K.2
Shimura, T.3
Hattori, T.4
Narita, S.5
Shiozawa, K.6
Ikeda, S.7
Uchiyama, K.8
-
64
-
-
0034863403
-
Enhanced Multi-Threshold (MTCMOS) Circuits Using Variable Well Bias
-
August
-
S. V. Kosonocky, M. Immediato, P. Cottrell, T. Hook, R. Mann, and J. Brown, "Enhanced Multi-Threshold (MTCMOS) Circuits Using Variable Well Bias," Proceedings of the ISLPED, August 2001, pp. 165-169.
-
(2001)
Proceedings of the ISLPED
, pp. 165-169
-
-
Kosonocky, S.V.1
Immediato, M.2
Cottrell, P.3
Hook, T.4
Mann, R.5
Brown, J.6
-
65
-
-
0029723245
-
A 0.8V/100MHz/Sub-5mW-Operated Mega-Bit SRAM Cell Architecture with Charge-Recycle Offset-Source Driving (OSD) Scheme
-
June
-
H. Yamauchi, T. Iwata, H. Akamatsu, and A. Matsuzawa, "A 0.8V/100MHz/Sub-5mW-Operated Mega-Bit SRAM Cell Architecture with Charge-Recycle Offset-Source Driving (OSD) Scheme," Symposium on VLSI Circuits, Digest of Technical Papers, June 1996, pp. 126-127.
-
(1996)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 126-127
-
-
Yamauchi, H.1
Iwata, T.2
Akamatsu, H.3
Matsuzawa, A.4
-
66
-
-
0034878684
-
Effectiveness of Reverse Body Bias for Leakage Control in Scaled Dual Vt CMOS ICs
-
August
-
A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar, and V. De, "Effectiveness of Reverse Body Bias for Leakage Control in Scaled Dual Vt CMOS ICs," Proceedings of the ISLPED, August 2001, pp. 207-212.
-
(2001)
Proceedings of the ISLPED
, pp. 207-212
-
-
Keshavarzi, A.1
Ma, S.2
Narendra, S.3
Bloechel, B.4
Mistry, K.5
Ghani, T.6
Borkar, S.7
De, V.8
-
67
-
-
0038306265
-
Zigzag Super Cut-Oft CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era
-
February
-
K.-S. Min, H. Kawaguchi, and T. Sakurai, "Zigzag Super Cut-Oft CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era," ISSCC Digest of Technical Papers, February 2003, pp. 400-401.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 400-401
-
-
Min, K.-S.1
Kawaguchi, H.2
Sakurai, T.3
-
70
-
-
0027699006
-
256-Mb DRAM Circuit Technologies for File Applications
-
November
-
G. Kitsukawa, M. Horiguchi, Y. Kawajiri, T. Kawahara, T. Akiba, Y. Kawase, T. Tachibana, T. Sakai, M. Aoki, S. Shukuri, K. Sagara, R. Nagai, Y. Ohji, N. Hasegawa, N. Yokoyama, T. Kisu, H. Yamashita, T. Kure, and T. Nishida, "256-Mb DRAM Circuit Technologies for File Applications," IEEE J. Solid-State Circuits 28, No. 11, 1105-1113 (November 1993).
-
(1993)
IEEE J. Solid-state Circuits
, vol.28
, Issue.11
, pp. 1105-1113
-
-
Kitsukawa, G.1
Horiguchi, M.2
Kawajiri, Y.3
Kawahara, T.4
Akiba, T.5
Kawase, Y.6
Tachibana, T.7
Sakai, T.8
Aoki, M.9
Shukuri, S.10
Sagara, K.11
Nagai, R.12
Ohji, Y.13
Hasegawa, N.14
Yokoyama, N.15
Kisu, T.16
Yamashita, H.17
Kure, T.18
Nishida, T.19
-
71
-
-
0346715583
-
Two-Dimensional Power-Line Selection Scheme for Low Subthreshold-Current Multi-Gigabit DRAMs
-
September
-
T. Sakata, M. Horiguchi, M. Aoki, and K. Itoh, "Two-Dimensional Power-Line Selection Scheme for Low Subthreshold-Current Multi-Gigabit DRAMs," Proceedings of the ESSCIRC, September 1993, pp. 131-134.
-
(1993)
Proceedings of the ESSCIRC
, pp. 131-134
-
-
Sakata, T.1
Horiguchi, M.2
Aoki, M.3
Itoh, K.4
-
72
-
-
0346715577
-
Mew Standby-Current Reduction Technique for Deep Sub-Micron VLSI CMOS Circuits: Smart Series Switch
-
September
-
P. R. van der Meer and A. van Staveren, "Mew Standby-Current Reduction Technique for Deep Sub-Micron VLSI CMOS Circuits: Smart Series Switch," Proceedings of the ESSCIRC, September 2002, pp. 663-666.
-
(2002)
Proceedings of the ESSCIRC
, pp. 663-666
-
-
Van der Meer, P.R.1
Van Staveren, A.2
-
73
-
-
0026404719
-
A Circuit Technology for Sub-10ns ECL 4Mb BiCMOS DRAMs
-
June
-
T. Kawahara, Y. Kawajiri, G. Kitsukawa, Y. Nakagome, K. Sagara, Y. Kawamoto, T. Akiba, S. Kato, Y. Kawase, and K. Itoh, "A Circuit Technology for Sub-10ns ECL 4Mb BiCMOS DRAMs," Symposium on VLSI Circuits, Digest of Technical Papers, June 1991, pp. 131-132.
-
(1991)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 131-132
-
-
Kawahara, T.1
Kawajiri, Y.2
Kitsukawa, G.3
Nakagome, Y.4
Sagara, K.5
Kawamoto, Y.6
Akiba, T.7
Kato, S.8
Kawase, Y.9
Itoh, K.10
-
74
-
-
0033682271
-
CMOS-Logic-Circuit-Compatible DRAM Circuit Designs for Wide-Voltage and Wide-Temperature-Range Applications
-
June
-
H. Mizuno, N. Oodaira, Y. Kanno, T. Sakata, and T. Watanabe, "CMOS-Logic-Circuit-Compatible DRAM Circuit Designs for Wide-Voltage and Wide-Temperature-Range Applications," Symposium on VLSI Circuits, Digest of Technical Papers, June 2000, pp. 120-121.
-
(2000)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 120-121
-
-
Mizuno, H.1
Oodaira, N.2
Kanno, Y.3
Sakata, T.4
Watanabe, T.5
-
75
-
-
0037630654
-
A 1.5V 1.7ns 4k×32 SRAM with a Fully-Differential Auto-Power-Down Current Sense Amplifier
-
February
-
B. Wicht, J.-Y. Larguier, and D. Schmitt-Landsiedel, "A 1.5V 1.7ns 4k×32 SRAM with a Fully-Differential Auto-Power-Down Current Sense Amplifier," ISSCC Digest of Technical Papers, February 2003, pp. 462-463.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 462-463
-
-
Wicht, B.1
Larguier, J.-Y.2
Schmitt-Landsiedel, D.3
-
76
-
-
0242611643
-
μI/O Architecture for 0.13-μm Wide-Voltage-Range System-on-a-Package (SoP) Designs
-
June
-
Y. Kanno, H. Mizuno, N. Oodaira, Y. Yasu, and K. Yanagisawa, "μI/O Architecture for 0.13-μm Wide-Voltage-Range System-on-a-Package (SoP) Designs," Symposium on VLSI Circuits, Digest of Technical Papers, June 2002, pp. 168-169.
-
(2002)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 168-169
-
-
Kanno, Y.1
Mizuno, H.2
Oodaira, N.3
Yasu, Y.4
Yanagisawa, K.5
-
77
-
-
0034849202
-
Level Shifters for High-Speed 1 V to 3.3 V Interfaces in a 0.13μm Cu-Interconnection/Low-k CMOS Technology
-
May
-
W. Wen-Tai, K. Ming-Dou, C. Mi-Chang, and C. Chung-Hui, "Level Shifters for High-Speed 1 V to 3.3 V Interfaces in a 0.13μm Cu-Interconnection/Low-k CMOS Technology," Proceedings of the International Symposium on VLSI Technology, Systems, and Applications, May 2001, pp. 307-310.
-
(2001)
Proceedings of the International Symposium on VLSI Technology, Systems, and Applications
, pp. 307-310
-
-
Wen-Tai, W.1
Ming-Dou, K.2
Mi-Chang, C.3
Chung-Hui, C.4
-
78
-
-
84941446360
-
Circuit Techniques for 1.5-3.6-V Battery-Operated 64-Mb DRAM
-
September
-
Y. Nakagome, K. Itoh, K. Takeuchi, E. Kume, H. Tanaka, M. Isoda, T. Musha, T. Kaga, T. Kisu, T. Nishida, Y. Kawamoto, and M. Aoki, "Circuit Techniques for 1.5-3.6-V Battery-Operated 64-Mb DRAM," Proceedings of the ESSCIRC, September 1990, pp. 157-160.
-
(1990)
Proceedings of the ESSCIRC
, pp. 157-160
-
-
Nakagome, Y.1
Itoh, K.2
Takeuchi, K.3
Kume, E.4
Tanaka, H.5
Isoda, M.6
Musha, T.7
Kaga, T.8
Kisu, T.9
Nishida, T.10
Kawamoto, Y.11
Aoki, M.12
-
79
-
-
0005115089
-
OX 1.8 V CMOS Technology
-
February
-
OX 1.8 V CMOS Technology," ISSCC Digest of Technical Papers, February 1999, pp. 276-277.
-
(1999)
ISSCC Digest of Technical Papers
, pp. 276-277
-
-
Sanchez, H.1
Siegel, J.2
Nicoletta, C.3
Alvarez, J.4
Nissen, J.5
Gerosa, G.6
-
80
-
-
0033221989
-
High-Voltage-Tolerant I/O Buffers with Low-Voltage CMOS Process
-
November
-
G. P. Singh and R. B. Salem, "High-Voltage-Tolerant I/O Buffers with Low-Voltage CMOS Process," IEEE J. Solid-State Circuits 34, No. 11, 1512-1525 (November 1999).
-
(1999)
IEEE J. Solid-state Circuits
, vol.34
, Issue.11
, pp. 1512-1525
-
-
Singh, G.P.1
Salem, R.B.2
-
81
-
-
0022252167
-
A 1Mb DRAM with 3-Dimensional Stacked Capacitor Cells
-
February
-
Y. Takemae, T. Ema, M. Nakano, F. Baba, T. Yabu, K. Miyasaki, and K. Shirai, "A 1Mb DRAM with 3-Dimensional Stacked Capacitor Cells," ISSCC Digest of Technical Papers, February 1985, pp. 250-251.
-
(1985)
ISSCC Digest of Technical Papers
, pp. 250-251
-
-
Takemae, Y.1
Ema, T.2
Nakano, M.3
Baba, F.4
Yabu, T.5
Miyasaki, K.6
Shirai, K.7
-
82
-
-
84943679346
-
A Threshold Voltage Controlling Circuit for Short Channel MOS Integrated Circuits
-
February
-
M. Kubo, R. Hori, O. Minato, and K. Sato, "A Threshold Voltage Controlling Circuit for Short Channel MOS Integrated Circuits," ISSCC Digest of Technical Papers, February 1976, pp. 54-55.
-
(1976)
ISSCC Digest of Technical Papers
, pp. 54-55
-
-
Kubo, M.1
Hori, R.2
Minato, O.3
Sato, K.4
-
83
-
-
84943735861
-
Substrate and Load Gate Voltage Compensation
-
February
-
E. M. Blaser, W. M. Chu, and G. Sonoda, "Substrate and Load Gate Voltage Compensation," ISSCC Digest of Technical Papers, February 1976, pp. 56-57.
-
(1976)
ISSCC Digest of Technical Papers
, pp. 56-57
-
-
Blaser, E.M.1
Chu, W.M.2
Sonoda, G.3
-
84
-
-
0031655062
-
A Sub-0.1μm Circuit Design with Substrate-Over-Biasing
-
February
-
Y. Oowaki, M. Noguchi, S. Takagi, D. Takashima, M. Ono, Y. Matsunaga, K. Sunouchi, H. Kawaguchiya, S. Matsuda, M. Kamoshida, T. Fuse, S. Watanabe, A. Toriumi, S. Manabe, and A. Hojo, "A Sub-0.1μm Circuit Design with Substrate-Over-Biasing," ISSCC Digest of Technical Papers, February 1998, pp. 88-89.
-
(1998)
ISSCC Digest of Technical Papers
, pp. 88-89
-
-
Oowaki, Y.1
Noguchi, M.2
Takagi, S.3
Takashima, D.4
Ono, M.5
Matsunaga, Y.6
Sunouchi, K.7
Kawaguchiya, H.8
Matsuda, S.9
Kamoshida, M.10
Fuse, T.11
Watanabe, S.12
Toriumi, A.13
Manabe, S.14
Hojo, A.15
-
85
-
-
0034430275
-
1000-MIPS/W Microprocessor Using Speed-Adaptive Threshold-Voltage CMOS with Forward Bias
-
February
-
M. Miyazaki, G. Ono, T. Hattori, K. Shiozawa, K. Uchiyama, and K. Ishibashi, "1000-MIPS/W Microprocessor Using Speed-Adaptive Threshold-Voltage CMOS with Forward Bias," ISSCC Digest of Technical Papers, February 2000, pp. 420-421.
-
(2000)
ISSCC Digest of Technical Papers
, pp. 420-421
-
-
Miyazaki, M.1
Ono, G.2
Hattori, T.3
Shiozawa, K.4
Uchiyama, K.5
Ishibashi, K.6
-
86
-
-
0037969263
-
A 9μW 50MHz 32b Adder Using a Self-Adjusted Forward Body Bias in SoCs
-
February
-
K. Ishibashi, T. Yamashita, Y. Arima, I. Minematsu, and T. Fujimoto, "A 9μW 50MHz 32b Adder Using a Self-Adjusted Forward Body Bias in SoCs," ISSCC Digest of Technical Papers, February 2003, pp. 116-117.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 116-117
-
-
Ishibashi, K.1
Yamashita, T.2
Arima, Y.3
Minematsu, I.4
Fujimoto, T.5
-
87
-
-
0037630711
-
Self-Corrective Device and Architecture to Ensure LSI Operation at 0.5V Using Bulk Dynamic Threshold MOSFET with a Self-Adaptive Power Supply
-
February
-
S. Kakimoto, T. Okuno, Y. Iwase, Y. Yaoi, F. Yoshioka, K. Kimoto, M. Nakano, K. Kawashima, S. Morishita, K. Sugimoto, T. Shiomi, T. Okumine, K. Kataoka, A. Shibata, S. Toyoyama, Y. Satoh, K. Fujimoto, K. Tatsumi, H. Kotaki, and A. Kito, "Self-Corrective Device and Architecture to Ensure LSI Operation at 0.5V Using Bulk Dynamic Threshold MOSFET with a Self-Adaptive Power Supply," ISSCC Digest of Technical Papers, February 2003, pp. 402-403.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 402-403
-
-
Kakimoto, S.1
Okuno, T.2
Iwase, Y.3
Yaoi, Y.4
Yoshioka, F.5
Kimoto, K.6
Nakano, M.7
Kawashima, K.8
Morishita, S.9
Sugimoto, K.10
Shiomi, T.11
Okumine, T.12
Kataoka, K.13
Shibata, A.14
Toyoyama, S.15
Satoh, Y.16
Fujimoto, K.17
Tatsumi, K.18
Kotaki, H.19
Kito, A.20
more..
-
88
-
-
0030081925
-
A 160 MHz 32 b 0.5 W CMOS RISC Microprocessor
-
February
-
J. Montanaro, R. T. Witek, K. Anne, A. J. Black, E. M. Cooper, D. W. Dobberpuhl, P. M. Donahue, J. Eno, A. Farell, G. W. Hoeppner, D. Kruckemyer, T. H. Lee, P. Lin, L. Madden, D. Murray, M. Pearce, S. Santhanam, K. J. Snyder, R. Stephany, and S. C. Thierauf, "A 160 MHz 32 b 0.5 W CMOS RISC Microprocessor," ISSCC Digest of Technical Papers, February 1996, pp. 214-215.
-
(1996)
ISSCC Digest of Technical Papers
, pp. 214-215
-
-
Montanaro, J.1
Witek, R.T.2
Anne, K.3
Black, A.J.4
Cooper, E.M.5
Dobberpuhl, D.W.6
Donahue, P.M.7
Eno, J.8
Farell, A.9
Hoeppner, G.W.10
Kruckemyer, D.11
Lee, T.H.12
Lin, P.13
Madden, L.14
Murray, D.15
Pearce, M.16
Santhanam, S.17
Snyder, K.J.18
Stephany, R.19
Thierauf, S.C.20
more..
-
89
-
-
0008802188
-
Transmeta's Crusoe: A Low-Power x86-Compatible Microprocessor Built with Software
-
April
-
D. R. Ditzel, "Transmeta's Crusoe: A Low-Power x86-Compatible Microprocessor Built with Software," presented at Cool Chips III, April 2000.
-
(2000)
Cool Chips III
-
-
Ditzel, D.R.1
-
90
-
-
0034430973
-
A Dynamic Voltage Scaled Microprocessor System
-
February
-
T. Burd, T. Pering, A. Stratakos, and R. Brodersen, "A Dynamic Voltage Scaled Microprocessor System," ISSCC Digest of Technical Papers, February 2000, pp. 294-295.
-
(2000)
ISSCC Digest of Technical Papers
, pp. 294-295
-
-
Burd, T.1
Pering, T.2
Stratakos, A.3
Brodersen, R.4
-
91
-
-
0035063733
-
ChipOS: Open Power-Management Platform to Overcome the Power Crisis in Future LSIs
-
February
-
H. Mizuno and T. Kawahara, "ChipOS: Open Power-Management Platform to Overcome the Power Crisis in Future LSIs," ISSCC Digest of Technical Papers, February 2001, pp. 344-345.
-
(2001)
ISSCC Digest of Technical Papers
, pp. 344-345
-
-
Mizuno, H.1
Kawahara, T.2
-
92
-
-
0034784787
-
Autonomous Decentralized Low-Power System LSI Using Self-Instructing Predictive Shutdown Method
-
June
-
T. Shimizu, F. Arakawa, and T. Kawahara, "Autonomous Decentralized Low-Power System LSI Using Self-Instructing Predictive Shutdown Method," Symposium on VLSI Circuits, Digest of Technical Papers, June 2001, pp. 55-56.
-
(2001)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 55-56
-
-
Shimizu, T.1
Arakawa, F.2
Kawahara, T.3
-
93
-
-
0037969270
-
An Autonomous Decentralized Low-Power System with Adaptive-Universal Control for a Chip Multi-Processor
-
February
-
M. Miyazaki, G. Ono, H. Tanaka, N. Ohkubo, and T. Kawahara, "An Autonomous Decentralized Low-Power System with Adaptive-Universal Control for a Chip Multi-Processor," ISSCC Digest of Technical Papers, February 2003, pp. 108-109.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 108-109
-
-
Miyazaki, M.1
Ono, G.2
Tanaka, H.3
Ohkubo, N.4
Kawahara, T.5
-
94
-
-
0034833289
-
Design Methodology of High Performance Microprocessor Using Ultra-Low Threshold Voltage CMOS
-
May
-
T. Miyake, T. Yamashita, N. Asari, H. Sekisaka, T. Sakai, K. Matsuura, A. Wakahara, H. Takahashi, T. Hiyama, K. Miyamoto, and K. Mori, "Design Methodology of High Performance Microprocessor Using Ultra-Low Threshold Voltage CMOS," Proceedings of the CICC, May 2001, pp. 275-278.
-
(2001)
Proceedings of the CICC
, pp. 275-278
-
-
Miyake, T.1
Yamashita, T.2
Asari, N.3
Sekisaka, H.4
Sakai, T.5
Matsuura, K.6
Wakahara, A.7
Takahashi, H.8
Hiyama, T.9
Miyamoto, K.10
Mori, K.11
-
95
-
-
0032025630
-
Supply Voltage Scaling for Temperature-Insensitive CMOS Circuit Operation
-
March
-
A. Bellaouar, A. Fridi, M. I. Elmasry, and K. Itoh, "Supply Voltage Scaling for Temperature-Insensitive CMOS Circuit Operation," IEEE Trans. Circuits & Syst. 45, 415-417 (March 1998).
-
(1998)
IEEE Trans. Circuits & Syst.
, vol.45
, pp. 415-417
-
-
Bellaouar, A.1
Fridi, A.2
Elmasry, M.I.3
Itoh, K.4
-
96
-
-
0035473305
-
Design Impact of Positive Temperature Dependence on Drain Current in Sub-1-V CMOS VLSIs
-
October
-
K. Kanda, K. Nose, H. Kawaguchi, and T. Sakurai, "Design Impact of Positive Temperature Dependence on Drain Current in Sub-1-V CMOS VLSIs," IEEE J. Solid-State Circuits 36, No. 10, 1559-1564 (October 2001).
-
(2001)
IEEE J. Solid-state Circuits
, vol.36
, Issue.10
, pp. 1559-1564
-
-
Kanda, K.1
Nose, K.2
Kawaguchi, H.3
Sakurai, T.4
-
97
-
-
0001499971
-
SOI for Digital CMOS LSI: Design Considerations and Advances
-
April
-
C. Chuang, P. Lu, and C. J. Anderson, "SOI for Digital CMOS LSI: Design Considerations and Advances," Proc. IEEE 66, No. 4, 689-720 (April 1998).
-
(1998)
Proc. IEEE
, vol.66
, Issue.4
, pp. 689-720
-
-
Chuang, C.1
Lu, P.2
Anderson, C.J.3
-
98
-
-
0035061386
-
A 900 MHz 2.25MB Cache with On-Chip CPU - Now in Cu SOI
-
February
-
J. M. Hill and J. Lachman, "A 900 MHz 2.25MB Cache with On-Chip CPU - Now in Cu SOI," ISSCC Digest of Technical Papers, February 2001, pp. 176-177.
-
(2001)
ISSCC Digest of Technical Papers
, pp. 176-177
-
-
Hill, J.M.1
Lachman, J.2
-
99
-
-
0242443402
-
High Performance SRAMs in 1.5V, .018μm Partially Depleted SOI
-
June
-
R. V. Joshi, A. Pellela, O. Wagner, Y. H. Chan, W. Dachtera, S. Wilson, and S. P. Kowalczyk, "High Performance SRAMs in 1.5V, .018μm Partially Depleted SOI," Symposium on VLSI Circuits, Digest of Technical Papers, June 2002, pp. 74-77.
-
(2002)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 74-77
-
-
Joshi, R.V.1
Pellela, A.2
Wagner, O.3
Chan, Y.H.4
Dachtera, W.5
Wilson, S.6
Kowalczyk, S.P.7
-
100
-
-
0036047590
-
High Soft-Error Tolerance Body-Tied SOI Technology
-
June
-
Y. Hirano, T. Iwamatsu, K. Shiga, K. Nii, K. Sonoda, T. Matsumoto, S. Maeda, Y. Yamaguchi, T. Ipposhi, S. Maegawa, and Y. Inoue, "High Soft-Error Tolerance Body-Tied SOI Technology," Symposium on VLSI Technology, Digest of Technical Papers, June 2002, pp. 48-49.
-
(2002)
Symposium on VLSI Technology, Digest of Technical Papers
, pp. 48-49
-
-
Hirano, Y.1
Iwamatsu, T.2
Shiga, K.3
Nii, K.4
Sonoda, K.5
Matsumoto, T.6
Maeda, S.7
Yamaguchi, Y.8
Ipposhi, T.9
Maegawa, S.10
Inoue, Y.11
-
101
-
-
0037631001
-
A 400MHz 183mW Microcontroller in Body-Tied SOI Technology
-
February
-
H. Sato, N. Itoh, K. Nii, K. Yoshida, Y. Nakase, H. Makino, A. Yamada, T. Arakawa, S. Iwade, Y. Hirano, and T. Ipposhi, "A 400MHz 183mW Microcontroller in Body-Tied SOI Technology," ISSCC Digest of Technical Papers, February 2003, pp. 110-111.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 110-111
-
-
Sato, H.1
Itoh, N.2
Nii, K.3
Yoshida, K.4
Nakase, Y.5
Makino, H.6
Yamada, A.7
Arakawa, T.8
Iwade, S.9
Hirano, Y.10
Ipposhi, T.11
-
102
-
-
0029481651
-
Leakage Mechanism Due to Floating Body and Countermeasure on Dynamic Retention Mode of SOI-DRAM
-
June
-
F. Morishita, K. Suma, M. Hirose, T. Tsuruda, Y. Yamaguchi, T. Eimori, T. Oashi, K. Arimoto, Y. Inoue, and T. Nishimura, "Leakage Mechanism Due to Floating Body and Countermeasure on Dynamic Retention Mode of SOI-DRAM," Symposium on VLSI Technology, Digest of Technical Papers, June 1995, pp. 141-142.
-
(1995)
Symposium on VLSI Technology, Digest of Technical Papers
, pp. 141-142
-
-
Morishita, F.1
Suma, K.2
Hirose, M.3
Tsuruda, T.4
Yamaguchi, Y.5
Eimori, T.6
Oashi, T.7
Arimoto, K.8
Inoue, Y.9
Nishimura, T.10
-
103
-
-
0036048291
-
An Embedded DRAM Technology on SOI/Bulk Hybrid Substrate Formed with SEG Process for High-End SOC Application
-
June
-
T. Yamada, K. Takahashi, H. Oyamatsu, H. Nagano, T. Sato, I. Mizushima, S. Nitta, T. Hojo, K. Kokubunn, K. Yasumoto, Y. Matsubara, T. Yoshida, S. Yamada, Y. Tsunashima, Y. Saito, S. Nadahara, Y. Katsumata, M. Yoshimi, and H. Ishiuchi, "An Embedded DRAM Technology on SOI/Bulk Hybrid Substrate Formed with SEG Process for High-End SOC Application," Symposium on VLSI Technology, Digest of Technical Papers, June 2002, pp. 112-113.
-
(2002)
Symposium on VLSI Technology, Digest of Technical Papers
, pp. 112-113
-
-
Yamada, T.1
Takahashi, K.2
Oyamatsu, H.3
Nagano, H.4
Sato, T.5
Mizushima, I.6
Nitta, S.7
Hojo, T.8
Kokubunn, K.9
Yasumoto, K.10
Matsubara, Y.11
Yoshida, T.12
Yamada, S.13
Tsunashima, Y.14
Saito, Y.15
Nadahara, S.16
Katsumata, Y.17
Yoshimi, M.18
Ishiuchi, H.19
-
104
-
-
0028736473
-
A Novel Silicon-On-Insulator (SOI) MOSFET for Ultra Low Voltage Operation
-
August
-
F. Assaderaghi, S. Parke, P. K. Ko, and C. Hu, "A Novel Silicon-On-Insulator (SOI) MOSFET for Ultra Low Voltage Operation," Proceedings of the ISLPED, August 1994, pp. 58-59.
-
(1994)
Proceedings of the ISLPED
, pp. 58-59
-
-
Assaderaghi, F.1
Parke, S.2
Ko, P.K.3
Hu, C.4
-
105
-
-
0242526956
-
Ultralow-Power CMOS/SOI LSI Design for Future Mobile Systems
-
June
-
T. Douseki, J. Yamada, and H. Kyuragi, "Ultralow-Power CMOS/SOI LSI Design for Future Mobile Systems," Symposium on VLSI Circuits, Digest of Technical Papers, June 2001, pp. 6-9.
-
(2001)
Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 6-9
-
-
Douseki, T.1
Yamada, J.2
Kyuragi, H.3
-
106
-
-
0038645532
-
TH FD-SOI Technology
-
February
-
TH FD-SOI Technology," ISSCC Digest of Technical Papers, February 2003, pp. 106-107.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 106-107
-
-
Kawaguchi, H.1
Kanda, K.2
Nose, K.3
Hattori, S.4
Antono, D.D.5
Yamada, D.6
Miyazaki, T.7
Inagaki, K.8
Hiramoto, T.9
Sakurai, T.10
-
107
-
-
0037630998
-
A 0.3V 3.6GHz 0.3mW Frequency Divider with Differential ED-CMOS/SOI Circuit Technology
-
February
-
T. Douseki, T. Shimamura, and N. Shibata, "A 0.3V 3.6GHz 0.3mW Frequency Divider with Differential ED-CMOS/SOI Circuit Technology," ISSCC Digest of Technical Papers, February 2003, pp. 114-115.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 114-115
-
-
Douseki, T.1
Shimamura, T.2
Shibata, N.3
-
108
-
-
0035445204
-
A Study of the Threshold Voltage Variation for Ultra-Small Bulk and SOI CMOS
-
September
-
K. Takeuchi, R. Koh, and T. Mogami, "A Study of the Threshold Voltage Variation for Ultra-Small Bulk and SOI CMOS," IEEE Trans. Electron Devices 48, No. 9, 1995-2001 (September 2001).
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, Issue.9
, pp. 1995-2001
-
-
Takeuchi, K.1
Koh, R.2
Mogami, T.3
-
109
-
-
0035714801
-
FD/DG-SOI MOSFET: A Viable Approach to Overcoming the Device Scaling Limit
-
December
-
D. Hisamoto, "FD/DG-SOI MOSFET: A Viable Approach to Overcoming the Device Scaling Limit," IEDM Tech, Digest, pp. 429-432 (December 2001).
-
(2001)
IEDM Tech, Digest
, pp. 429-432
-
-
Hisamoto, D.1
-
110
-
-
0036923594
-
Metal-Gate FinFET and Fully-Depleted SOI Devices Using Total Gate Silicidation
-
December
-
J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Kanaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, and W. Haensch, "Metal-Gate FinFET and Fully-Depleted SOI Devices Using Total Gate Silicidation," IEDM Tech. Digest, pp. 247-250 (December 2002).
-
(2002)
IEDM Tech. Digest
, pp. 247-250
-
-
Kedzierski, J.1
Nowak, E.2
Kanarsky, T.3
Zhang, Y.4
Boyd, D.5
Carruthers, R.6
Cabral, C.7
Amos, R.8
Lavoie, C.9
Roy, R.10
Newbury, J.11
Sullivan, E.12
Benedict, J.13
Saunders, P.14
Wong, K.15
Kanaperi, D.16
Krishnan, M.17
Lee, K.-L.18
Rainey, B.A.19
Fried, D.20
Cottrell, P.21
Wong, H.-S.P.22
Ieong, M.23
Haensch, W.24
more..
-
111
-
-
0031079417
-
Scaling Theory for Cylindrical, Fully Depleted Surrounding Gate MOSFETs
-
February
-
C. P. Auth and J. D. Plummer, "Scaling Theory for Cylindrical, Fully Depleted Surrounding Gate MOSFETs," IEEE Electron Device Lett. 18, 74-76 (February 1997).
-
(1997)
IEEE Electron Device Lett.
, vol.18
, pp. 74-76
-
-
Auth, C.P.1
Plummer, J.D.2
-
113
-
-
0035054710
-
A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM
-
February
-
P. K. Naji, M. Durlam, S. Tehrani, J. Calder, and M. F. DeHerrera, "A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM," ISSCC Digest of Technical Papers, February 2001, pp. 122-123.
-
(2001)
ISSCC Digest of Technical Papers
, pp. 122-123
-
-
Naji, P.K.1
Durlam, M.2
Tehrani, S.3
Calder, J.4
Deherrera, M.F.5
-
114
-
-
0036110780
-
Ovonic Unified Memory: A High-Performance Nonvolatile Memory Technology for Stand-Alone Memory and Embedded Applications
-
February
-
M. Gill, T. Lowrey, and J. Park, "Ovonic Unified Memory: A High-Performance Nonvolatile Memory Technology for Stand-Alone Memory and Embedded Applications," ISSCC Digest of Technical Papers, February 2002. pp. 202-203.
-
(2002)
ISSCC Digest of Technical Papers
, pp. 202-203
-
-
Gill, M.1
Lowrey, T.2
Park, J.3
|