A 1.5V 1.7ns 4k × 32 SRAM with a fully-differential auto-power-down current sense amplifier

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Wicht, Bernhard ^a   Larguier, Jean Yves ^b   Schmitt Landsiedel, Doris ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATOR CIRCUITS; DIFFERENTIAL AMPLIFIERS; FEEDBACK AMPLIFIERS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; RANDOM ACCESS STORAGE; TRANSISTORS;

CURRENT SENSE AMPLIFIER; DIFFERENTIAL FEEDBACK AMPLIFIER; SHMOO PLOT; SYNCHRONOUS RANDOM ACCESS MEMORY; VOLTAGE SENSE AMPLIFIER;

CMOS INTEGRATED CIRCUITS;

EID: 0037630654     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Seevinck, E., et al., "Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's," IEEE JSSC, vol. 26, no. 4, pp. 525-536, April 1991
2. Shibata, N., "Current Sensor Amplifiers for Low-Voltage Memories," IEICE Trans. Electron., vol. E79-C, No. 8, pp. 120-30, Aug. 1996
3. Wicht, B., et al., "SRAM Current-Sense Amplifier with Fully-Compensated Bit Line Multiplexer," ISSCC Dig. Techn. Papers, 2001, pp. 172-173, 443, 444.
4. Wicht, B., et al., "Analysis and Compensation of the Bitline Multiplexer in SRAM Current Sense Amplifiers," IEEE JSSC, vol. 36, no. 11, pp. 1745-1755, Nov. 2001.
5. Ishibashi, K., et al., "A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers," IEEE JSSC, vol. 30, no. 4, pp. 480-486, April 1995
6. Kobayashi, T., et al., "A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture," IEEE JSSC, vol. 28, no. 4, pp. 523-527, Apr. 1993.