Self-corrective device and architecture to ensure LSI operation at 0.5 V using bulk dynamic threshold MOSFET with a self-adaptive power supply

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Kakimoto, Seizo ^a   Okuno, Tomohisa ^a   Iwase, Yasuaki ^a   Yaoi, Yoshifumi ^a   Yoshioka, Fumiyoshi ^a   Kimoto, Kenji ^a   Nakano, Masayuki ^a   Kawashima, Kenji ^a   Morishita, Satoshi ^a   Sugimoto, Kazuo ^a   Shiomi, Takeshi ^a   Okumime, Tetsuya ^a   Kataoka, Kohtaroh ^a   Shibata, Akihide ^a   Toyoyama, Shinji ^a   Satoh, Yuhichi ^a   Fujimoto, Kazuya ^b   Tatsumi, Kenji ^b   Kotaki, Hiroshi ^a   Kito, Atsunori ^a  

^a SHARP CORPORATION   (Japan)

^b Integrated Circuit Group   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE CONTROL SYSTEMS; BIPOLAR TRANSISTORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LSI CIRCUITS; VOLTAGE CONTROL;

BULK DYNAMIC THRESHOLD; GATE ARRAY; INTERCONNECT ABILITY; POWER DISSIPATION; SELF-ADAPTIVE POWER SUPPLY SYSTEM; SELF-CORRECTIVE ARCHITECTURE; SELF-CORRECTIVE DEVICE;

MOSFET DEVICES;

EID: 0037630711     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. International Technology Roadmap for Semiconductors, 2001 edition
2. F. Assaderaaghi et al., "A Dynamic Threshold Voltage MOSFET (DTMOS) for Low Voltage Operation," IEEE Electron Device Lett., 15, pp.510-(1994).
3. H. Kotaki et al., "Novel Low Capacitance Sidewall Elevated Drain Dynamic Threshold Voltage MOSFET (LCSED) for Ultra Low Power Dual Gate CMOS Technology," 1998 Int. Electron Devices Meeting Tech. Dig., pp. 415-(1998)
4. T. Kuroda et al., "Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design," IEEE Journal of Solid-State Circuits, Vol.33, No.3, pp.454-462 (1998)