A low-impedance open-bitline array for multigigabit DRAM

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 4, 2002, Pages 487-498

  Sekiguchi, Tomonori ^a,b   Itoh, Kiyoo ^a,b   Takahashi, Tsugio ^a,c   Sugaya, Masahiro ^b   Fujisawa, Hiroki ^a,c   Nakamura, Masayuki ^a,c   Kajigaya, Kazuhiko ^c   Kimura, Katsutaka ^a,b  

^a IEEE   (Japan)

^b HITACHI LTD   (Japan)

^c Elpida Memory Inc   (Japan)

Author keywords

DRAM; Memory cell layout; Noise analysis; Noise reduction; Open bitline array

Indexed keywords

FOLDED BITLINE ARRAY; MEMORY CELL LAYOUT; MEMORY CELLS; MULTIGIGABIT GENERATION; NOISE ANALYSIS; OPEN BITLINE ARRAY; PRECHARGE NOISE; SENSE AMPLIFIERS; SENSING NOISE; STORAGE NODE CONTACTS;

COMPUTER SIMULATION; ELECTRIC CONDUCTIVITY OF SOLIDS; ELECTRIC IMPEDANCE; INTEGRATED CIRCUIT LAYOUT; NOISE ABATEMENT; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SPURIOUS SIGNAL NOISE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0036539318     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.991387     Document Type: Article

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