μI/O architecture for 0.13-μm wide-voltage-range system-on-a-package (SoP) designs

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 168-169

  Kanno, Y ^a   Mizuno, Hiroyuki ^a   Oodaira, Nobuhiro ^a   Yasu, Yoshihiko ^a   Yanagisawa, Kazumasa ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC IMPEDANCE; ELECTRIC POTENTIAL; ELECTRONICS PACKAGING; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; MULTICHIP MODULES; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

MULTI-CHIP PACKAGE; POWER SWITCH CONTROLLER; SYSTEM-ON-A-PACKAGE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0242611643     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. M. Hamada et al., 2001 CICC, pp.89-92, May 2001.
2. Y. Kanno et al., 2000 VLSI Symp., pp. 202-203, June 2000.
3. T. Inukai et al., 1999 SSDM, pp. 264-265, Sept. 1999.