Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: An alternative to clock-gating scheme in leakage dominant era

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Min, Kyeong Sik ^a   Kawaguchi, Hiroshi ^a   Sakurai, Takayasu ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; ELECTRIC CURRENTS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; TECHNOLOGY; VOLTAGE CONTROL;

BLOCK ACTIVATION; CLOCK-GATING SCHEME; HIGH-VOLTAGE STRESS; LEAKAGE POWER; LEAKAGE SUPPRESSION; ZIGZAG BOOSTED GATE; ZIGZAG SUPER CUT-OFF CMOS;

CMOS INTEGRATED CIRCUITS;

EID: 0038306265     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. H. Kawaguchi et al., IEEE J. Solid State Circuits, vol. 35, pp. 1498-1501, Oct. 2000.
2. K. Min et al., 28th European Solid-State Circuits Conference, pp. 679-682, Sep. 2002.
3. M. Horiguchi et al., IEEE J. Solid State Circuits, vol. 28, pp. 1131-1135, Nov. 1993.
4. Y. Nakagome et al., IEEE J. Solid State Circuits, vol. 26, pp. 1003-1010, July 1991.
5. Berkeley Predictive Technology Model web site (BPTM)