A 0.3V 3.6GHz 0.3mW frequency divider with differential ED-CMOS/SOI circuit technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Douseki, Takakuni ^a   Shimamura, Toshishige ^a   Shibata, Nobutaro ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FLIP FLOP CIRCUITS; LEAKAGE CURRENTS; LOGIC CIRCUITS; LSI CIRCUITS; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; ULTRATHIN FILMS;

BACK GATE BIAS; FREQUENCY DIVIDER; POWER DISSIPATION; TRIGGER FLIP FLOP;

CMOS INTEGRATED CIRCUITS;

EID: 0037630998     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. T. Douseki, et. al., "A 0.5V, Over 1GHz, 1mW MUX/DEMUX Core with Multi-Threshold Zero-Vth CMOS/SIMOX Technology," in Extended Abstract, SSDM, pp. 264-265, 2001.
2. H. Wang, et al., "A 1.8V 3mW 16.8GHz Frequency Divider in 0.25μm CMOS," ISSCC Dig. Tech. Papers, pp. 196-197, 2000.
3. B. Razavi, et. al., "Design of High-Speed, Low-Power Frequency Dividers and Phase-Locked Loops in Deep Sub-micron CMOS," IEEE JSSC, vol. 30, pp. 101-108, Feb. 1995.
4. J. M. C. Wong, et. al., "A 1-V 2.5mW 5.2GHz Frequency Divider in a 0.35-mm CMOS Process," 2002 Symp. on VLSI Circuits, pp. 190-191, 2002.