Leakage-biased domino circuits for dynamic fine-grain leakage reduction

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 316-319

  Heo, Seongmoo ^a   Asanović, Krste ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; LEAKAGE CURRENTS; LOGIC DESIGN; LOGIC GATES;

DYNAMICALLY-DEACTIVATED FAST TRANSISTORS; LEAKAGE-BIASED DOMINO CIRCUITS;

ADDERS;

EID: 0242526897     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (24)

1. M. W. Allam, M. H. Anis, and M. I. Elmastry. High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies. In ISLPED, pages 155-160, 2000.
2. Device Group at UC Berkeley. Predictive technology model. Technical report, PTM, 2001.
3. A. Chandrakasan, W. J. Bowhill, and F. Fox. Design of High Performance Microprocessor Circuits. IEEE Press, 2000.
4. V. De and S. Borkar. Technology and design challenges for low power and high performance. In ISLPED, pages 163-168, 1999.
5. A. Keshavarzi et al. Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. In ISLPED, pages 207-212, August 2001.
6. H. Makino et al. An auto-backgate-controlled MT-CMOS circuit. In Symp. on VLSI Circuits, pages 42-43, 1998.
7. J. Montanaro et al. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE JSSC, 31(11):1703-1714, November 1996.
8. K. Usami et al. Automated low-power technique exploiting multiple supply voltages applied to a media processor. IEEE JSSC, 33(3):463-471, March 1998.
9. L. Wei et al. Design and optimization of low voltage high performance dual threshold CMOS circuits. In DAC, pages 489-494, 1998.
10. M. Takahasi et al. A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. IEEE JSSC, 33(11):1772-1778, November 1998.
11. S. Geissler et al. A low-power RISC microprocessor using dual PLLs in a 0.13 μm SOI technology with copper interconnect and low-k BEOL dielectric. In ISSCC, February 2002.
12. S. K. Mathew et al. Sub-500-ps 64-b ALUs in 0.18 μm SOI/bulk CMOS: Design and scaling trends. IEEE JSSC, 36(11):1636-1646, November 2001.
13. S. Mutoh et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE JSSC, 30(8):847-854, August 1995.
14. S. Narendra et al. Scaling of stack effect and its application for leakage reduction. In ISLPED, pages 195-200, August 2001.
15. S, Shigematsu et al. A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. IEEE JSSC, 32(6):861-869, June 1997.
16. S. V. Kosonocky et al. Enhanced multi-threshold (MTCMOS) circuits using variable well bias. In ISLPED, pages 165-169, August 2001.
17. 2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. IEEE JSSC, 31(11):1770-1779, November 1996.
18. T.Kuroda et al. Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE JSSC, 33(3):454-462, March 1998.
19. T. McPherson et al. 760 MHz G6 S/390 microprocessor exploiting multiple Vt and copper interconnects. In ISSCC, pages 96-97, 2000.
20. W. Lee et al. A 1-V programmable DSP for wireless communications. IEEE JSSC, 32(11):1766-1766, November 1997.
21. J. P. Halter and F. Najm. A gate-level leakage power reduction method for ultra-low-power CMOS circuits. In CICC, pages 457-478, 1997.
22. T. Inukai. Boosted Gate MOS (BGMOS): Device/circuit cooperation scheme to achieve leakage-free giga-scale integration. In CICC, pages 409-412, 2000.
23. J. T. Kao and A. P. Chandrakasan. Dual-threshold voltage techniques for low-power digital circuits. IEEE JSSC, 35(7):1009-1018, July 2000.
24. Y. Ye, S. Borker, and V. De. A technique for standby leakage reduction in high-performance circuits. In Symp. on VLSI Circuits, pages 40-41, 1998.