A 9μW 50MHz 32b adder using a self-adjusted forward body bias in SoCs

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Ishibashi, Koichiro ^a   Yamashita, Takahiro ^a   Arima, Yukio ^a   Minematsu, Isao ^a   Fujimoto, Tetsuya ^a  

^a STARC   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CONTROL EQUIPMENT; ELECTRIC POWER SUPPLIES TO APPARATUS; NUMERICAL METHODS; TEMPERATURE; THRESHOLD VOLTAGE;

BODY BIAS CONTROLLER; SELF ADJUSTED FORWARD BODY BIAS; SYSTEM ON A CHIP;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037969263     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. T. Fuse et al., "A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic," ISSCC Dig. Tech. Papers, pp. 286-287, 1997.
2. S. Narendra et al. "1.1V 1GHz Communications Router with On-Chip Body Bias in 150nm CMOS," ISSCC Dig. Tech. Papers, pp. 270-271, 2002.
3. K. Kanda et al. "Design Impact of Positive Temperature Dependence of Drain Current in Sub-1-V CMOS VLSIs," IEEE J. Solid State Circuits, p.1559, Oct. 2001.
4. M. Miyazaki et al., "A 1000-MIPS/W Microprocessor using Speed-Adaptive Threshold-Voltage CMOS with Forward Bias," ISSCC Dig Techn. Papers, pp. 420-421, 2000.
5. http://www.jeita.or.jp/eiaj/english/news/pre39.htm