0.8V/100MHz/sub-5mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1996, Pages 126-127

  Yamauchi, Hiroyuki ^a   Iwata, Toru ^a   Akamatsu, Hironori ^a   Matsuzawa, Akira ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CHARGE; ELECTRIC DISCHARGES; ELECTRIC LOSSES; ELECTRIC VARIABLES MEASUREMENT; LEAKAGE CURRENTS; TRANSISTORS;

BITLINE ACCESS DELAY; CHARGE RECYCLE OFFSET SOURCE DRIVING SCHEME; CHARGE RECYCLING SOURCE CONTROL; PSEUD CROSS POINT ACCESS; PUMPING CIRCUIT; THRESHOLD VOLTAGE;

RANDOM ACCESS STORAGE;

EID: 0029723245     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)