Sub-0.1 μm circuit design with substrate-over-biasing

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 88-89,-420

  Oowaki, Y ^a   Noguchi, M ^a   Takagi, S ^a   Takashima, D ^a   Ono, M ^a   Matsunaga, Y ^a   Sunouchi, K ^a   Kawaguchiya, H ^a   Matsuda, S ^a   Kamoshida, M ^a   Fuse, T ^a   Watanabe, S ^a   Toriumi, A ^a   Manabe, S ^a   Hojo, A ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC GATES; SCHEMATIC DIAGRAMS; SUBSTRATES; TIMING CIRCUITS;

SUBSTRATE OVER BIASING;

LSI CIRCUITS;

EID: 0031655062     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)