A 1000-MIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 420-421

  Miyazaki, M ^a   Ono, G ^a   Hattori, T ^a   Shiozawa, K ^a   Uchiyama, K ^a   Ishibashi, K ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LSI CIRCUITS; MOSFET DEVICES; OSCILLATORS (ELECTRONIC); STATISTICAL METHODS; SUBSTRATES; THRESHOLD VOLTAGE;

RING OSCILLATORS;

MICROPROCESSOR CHIPS;

EID: 0034430275     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Performance fluctuations of 0.10μm MOSFETs - Limitation of 0.1mm ULSIs
2. 2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme
3. A 200mV self-testing encoder/decoder using stanford ultra-low-power CMOS
4. A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS for low voltage LSIs
5. A 18μa-standby-current 1.8V 200MHz microprocessor with self substrate-biased data-retention mode
6. Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation
7. A sub-0.1μm circuit design with substrate-over-biasing