A 400MHz 183mW microcontroller in body-tied SOI technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Sato, Hisakazu ^a   Itoh, Niichi ^a   Nii, Koji ^a   Yoshida, Kanako ^a   Nakase, Yasunobu ^a   Makino, Hiroshi ^a   Yamada, Akira ^a   Arakawa, Takahiko ^a   Iwade, Shuhei ^a   Hirano, Yuuichi ^a   Ipposhi, Takashi ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; MICROCONTROLLERS; RANDOM ACCESS STORAGE;

LOAD CAPACITANCE; PARTIAL TRENCH ISOLATION TECHNIQUE; STATIC TIMING ANALYZER;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0037631001     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. Y. Hirano, et al., "Impact of 0.10μm SOI CMOS with Body-Tied Hybrid Trench Isolation Structure to Bread Trough the Scaling Crisis of Silicon Technology," IEDM Tech. Dig., pp.467-470, 2000
2. A. Yamada, et al., "A 400 MHz RISC Microprocessor," Proc. COOL Chips V Conf., pp.257-267, 2002