Surrounding gate select transistor for 4F2 stacked Gbit DRAM

European Solid-State Device Research Conference

Volumn , Issue , 2001, Pages 131-134

  Hofmann, F ^a   Rosner W ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

SELECT TRANSISTOR; SURROUNDING-GATE;

EID: 77950265795     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2001.195218     Document Type: Conference Paper

References (4)

1. U. Aoki et al.'Tully Self-Aligned 6F2 Cell Technology for Low Cost 1Gb DRAM", Toshiba, VLSI Tech. Digest 1996, pp 22-23.
2. U. Gruening et al. "A Novel Trench DRAM Cell with a Vertical Access Transistor and Buried Strap for 4Gb", Infineon Technologies, IEDM Proceedings 1999, pp 25-28.
3. C. Radens et al. "A 0.135 um2 6F2 Trench-Sidewall Vertical Device Cell for 4Gb DRAM", IBM/Infineon Technologies, VLSI Tech. Digest, 2000, p80.
4. F. Hofmann et al. " CVD-EPI MOS Transistors with a 65 nm Vertical Channel", Siemens, Solid State Devices and Materials 1995, pp 46-48.