Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 10, 2002, Pages 1356-1360

  Hong, Sanghoon ^b   Kim, Sejun ^b   Wee, Jae Kyung ^a,c   Lee, Seongsoo ^a,d  

^a Hynix Semiconductor ^*

^b Hynix Semiconductor Inc   (South Korea)

^c Hallym University   (South Korea)

^d Soongsil University   (South Korea)

Author keywords

Data retention time; Offset cancellation sense amplifier scheme; Sensing margin

Indexed keywords

AMPLIFIERS (ELECTRONIC); DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC POWER SUPPLIES TO APPARATUS; VOLTAGE CONTROL; VOLTAGE MEASUREMENT;

DATA RETENTION TIME; LOW POWER COMPATIBILITY; LOW POWER DISSIPATION; OFFSET CANCELLATION SENSE AMPLIFIER;

CMOS INTEGRATED CIRCUITS;

EID: 0036772398     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.803052     Document Type: Article

References (3)

1. Y. Watanabe, N. Nakamura, and S. Watanabe, "Offset-compensating bitline sensing scheme for high-density DRAMs," IEEE J. Solid-State Circuits, vol. 29, pp. 9-13, Jan. 1994.
2. D. Min and D. W. Langer, "Multiple twisted dataline techniques for multigigabit DRAMs," IEEE J. Solid-State Circuits, vol. 34, pp. 856-865, June 1999.
3. K. Lim, S. Kang, J. Choi, J. Joo, Y. Lee, J. Lee, S. Cho, and B. Ryu, "Bitline coupling scheme and electrical fuse circuit for reliable operation of high-density DRAM," in Proc. VLSI Circuits Symp., June 2001, pp. 33-34.