A 1.0V 256Mb SDRAM with offset-compensated direct sensing and charge-recycled precharge schemes

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Sim, J Y ^a   Kwon, K W ^a   Choi, J H ^a   Lee, S H ^a   Kim, D M ^a   Hwang, H R ^a   Chun, K C ^a   Seo, Y H ^a   Hwang, H S ^a   Seo, D I ^a   Kim, C ^a   Cho, S I ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIFFERENTIAL AMPLIFIERS; ELECTRIC CURRENT CONTROL; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MOSFET DEVICES; POLYSILICON; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

BIT LINE SENSE AMPLIFIER; CHARGE RECYCLED PRECHARGE SCHEMES; COLUMN LINE SELECT; OFFSET COMPENSATED BIT LINE SENSING SCHEME; OFFSET COMPENSATED DIRECT SENSING; SHARED BIAS BRANCH SCHEME; STATIC RANDOM ACCESS MEMORY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0038306336     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Y. Watanabe, et. al., "Offset compensating bit-line sensing scheme for high density DRAM's," J. Solid State Circuits, vol. 28, pp. 9-13, Jan. 1994
2. S. H. Hong, et. al., "An offset cancellation bit-line sensing scheme for low-voltage DRAM applications," ISSCC Dig. Tech. Papers, pp. 154-155, 2002
3. Y. Yokoyama, et. al., "A 1.8-V embedded 18-Mb DRAM Macro with a 9-ns RAS access time and memory-cell area efficiency of 33%," J. Solid State Circuits, vol. 35. pp.503-509, Mar. 2001
4. T. Nagai, et. al., "A 17-ns 4-Mb CMOS DRAM," J. Solid State Circuits, vol. 25, pp. 1538-1543, Nov. 1991