The on-chip 3MB subarray based 3rd level cache on an Itanium microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 112-113+451+99

  Weiss, Don ^a   Wuu, John J ^a   Chin, Victor ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; FIELD EFFECT TRANSISTORS; FLIP FLOP CIRCUITS; PROM; STATIC RANDOM ACCESS STORAGE;

ERASABLE PROGRAMMABLE READ ONLY MEMORY (EPROM);

MICROPROCESSOR CHIPS;

EID: 0036116198     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. The implementation of the next-generation 64b Itanium microprocessor
2. A 450MHz 512kB second-level cache with a 3.6GB/s data bandwidth