A 300 MHz multi-banked eDRAM macro featuring GND sense, bit-line twisting and direct reference cell write

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 156-157+151

  Barth, John ^a   Anand, Darren ^a   Dreibelbis, Jeff ^a   Nelson, Erik ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAPACITANCE; CHARGE TRANSFER; OPTIMIZATION; PROBABILITY; STATIC RANDOM ACCESS STORAGE;

MOST SIGNIFICANT BIT (MSB);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0036116460     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. An ASIC library granular DRAM macro with built-in self test
2. A configurable dram macro design for 2112 derivative organizations to be synthesized using a memory generator
3. Processor based built-in self test for embedded DRAM
4. Integration of trench DRAM into a high performance 0.18 μm logic technology with copper BEOL