A 1.2V 1.5Gb/s 72Mb DDR3 SRAM

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 299-301+494

  Cho, Uk Rae ^a   Kim, Tae Hyoung ^a   Yoon, Yong Jin ^a   Lee, Jong Cheol ^a   Bae, Dae Gi ^a   Kim, Nam Seog ^a   Kim, Kang Young ^a   Son, Young Jae ^a   Yang, Jeong Suk ^a   Sohn, Kwon Il ^a   Kim, Sung Tae ^a   Lee, In Yeol ^a   Lee, Kwang Jin ^a   Kang, Tae Gyoung ^a   Kim, Su Chul ^a   Ahn, Kee Sik ^a   Byun, Hyun Geun ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; DECODING; ELECTRIC IMPEDANCE; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; PHASE SHIFT; VOLTAGE CONTROL;

CENTER TAPPED TERMINATION; CLOCK ADJUSTMENT CIRCUITS; DETECTION CIRCUIT; DOUBLE DATA RATE; DYNAMIC SELF RESETTING CIRCUITS; MAIN DATA LINES; POWER DISSIPATION; SENSE AMPLIFIER;

STATIC RANDOM ACCESS STORAGE;

EID: 0037630808     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Chappell, T., et al., "A 2-ns Cycle, 3.8-ns Access 512-kb CMOS ECL SRAM with a Fully Pipelined Architecture," IEEE J. of Solid-State Circuits, pp. 1577-1584, Nov., 1991.
2. Harold Pilo, et al., "An 833MHz 1.5W 18Mb CMOS SRAM with 1.67Gb/s/pin," ISSCC Digest of Technical Papers, pp. 266-267; Feb., 2000
3. Park, H-C., et al., "A 833Mb/s 2.5V 4Mb double data rate SRAM," ISSCC Digest of Technical Papers, pp. 356-357, 464; Feb., 1998.