SCOPUS 정보 검색 플랫폼

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 11, 1999, Pages 1512-1525

High-voltage-tolerant I/O buffers with low-voltage CMOS process

(2) Singh, Gajendra P a,b Salem, Raoul B a,c,d

a SUN MICROSYSTEMS (United States)

b National Informatics Centre (India)

c Microlectron Div Sun M (United States)

d Intergraph Adv Processor Division (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; MOSFET DEVICES; RANDOM ACCESS STORAGE; TRANSIENTS;

GATE-OXIDE STRESS; HIGH-VOLTAGE-TOLERANT INPUT/OUTPUT BUFFERS; STATIC RANDOM ACCESS MEMORY (SRAM);

BUFFER STORAGE;

EID: 0033221989 PISSN: 00189200 EISSN: None Source Type: Journal
DOI: 10.1109/4.799855 Document Type: Article

Times cited : (72)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.