500-MHz pipelined burst SRAM with improved SER immunity

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 11, 1999, Pages 1571-1579

  Sato, Hirotoshi ^a   Wada, Tomohisa ^a,b   Ohbayashi, Shigeki ^a   Kozaru, Kunihiko ^a   Okamoto, Yasuyuki ^a   Higashide, Yoshiko ^a   Shimizu, Tadayuki ^a   Maki, Yukio ^a   Morimoto, Rui ^a   Otoi, Hisakazu ^a   Koga, Tsuyoshi ^a   Honda, Hiroki ^a   Taniguchi, Makoto ^a   Arita, Yutaka ^a   Shiomi, Toru ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

^b UNIVERSITY OF THE RYUKYUS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DIES; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS; SYNCHRONIZATION; TRANSISTORS;

SOFT ERROR RATE (SER); STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 17144462799     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.799865     Document Type: Article

References (3)

1. G. Braceras, D. Evans, J. Sousa, and J. Connor, "A 350 MHz 3.3 V 4 Mb SRAM fabricated in a 0.3 μm CMOS process," in ISSCC Dig. Tech. Papers, Feb. 1997, pp. 404-405.
2. J. F. Ziegler, H. W. Curtis, F. P. Muhlfeld, C. J. Montrose, B. Chin, M. Nicewicz, C. A. Russell, W. Y. Wang, L. B. Freeman, P. Hosier, L. E. LaFave, J. L. Walsh, J. M. Orro, G. J. Unger, J. M. Ross, T. J. O'Gorman, B. Messina, T. D. Sullivan, A. J. Sykes, H. Yourke, T. A. Enger, V. Tolat, T. S. Scott, A. H. Taber, R. J. Sussman, W. A. Klein, and C. W. Wahaus, "IBM experiments in soft fails in computer electronics (1978-1994)," IBM J. Res. Develop., vol. 40, no. 1, pp. 3-18, 1996.
3. T. Shiomi, T. Wada, S. Ohbayashi, A. Ohba, H. Honda, Y. Ishigaki, S. Hine, K. Anami, K. Suzuki, and T. Sumi, "A 5.8 ns 256K BiCMOS TTL SRAM with T-shaped bit line architecture," IEEE J. Solid-State Circuits, vol. 28, pp. 1362-1369, Dec. 1993.