Level shifters for high-speed 1-V to 3.3-V interfaces in a 0.13-μm Cu-interconnection/low-k CMOS technology

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2001, Pages 307-310

  Wang, W T ^a   Ker, M D ^a   Chiang, M C ^a   Chen, C H ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

INTERCONNECTION NETWORKS; MASKS; MOSFET DEVICES; THRESHOLD VOLTAGE;

LEVEL SHIFTERS;

CMOS INTEGRATED CIRCUITS;

EID: 0034849202     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A high-voltage output buffer fabricated on a 2V CMOS technology
2. A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm, 3.5-nm Tox, 1.8-V CMOS technology
3. Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs
4. Static-noise margin analysis of MOS SRAM cells
5. A 0.13μm CMOS technology with 193nm lithography and Cu/low-k for high performance applications