Planar 1T-cell DRAM with MOS storage capacitors in a 130nm logic technology for high density microprocessors caches

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 127-130

  Somasekhar, Dinesh ^a   Lu, Shih Lien ^a   Bloechel, Bradley ^a   Lai, Konrad ^a   Borkar, Shekhar ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCUMULATION MODES; DEPLETION MODES; INVERSION MODES; LOGIC TECHNOLOGY; PLANAR MOS CAPACITORS; POWER DENSITIES; PROCESS ENHANCEMENTS; STORAGE CAPACITOR;

MOS CAPACITORS; STATIC RANDOM ACCESS STORAGE; T-CELLS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0346085073     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. W. Leung et al., "The Ideal SOC Memory: 1T-SRAM", in Proc. of the 2000 International ASIC/SOC Conf., pp. 32-36.
2. S. Tyagi et al., "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects", 2000 IEDM, pp. 567-570.
3. J-W. Sub et al., "Offset-trimming bit-line sensing scheme for gigabit-scale DRAM's", IEEE JSSC, vol.31 no.7, 1996, pp. 1025-1028.