High performance SRAMs in 1.5 V, 0.18μm partially depleted SOI technology

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 74-77

  Joshi, R V ^a   Pellela, A ^b   Wagner, O ^b   Chan, Y H ^b   Dachtera, W ^b   Wilson, S ^b   Kowalczyk, S P ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BUFFER STORAGE; BUILT-IN SELF TEST; LEAKAGE CURRENTS; PERFORMANCE; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY;

ACCESS TIME; ARRAY BUILT IN SELF TEST; CYCLE TIME; PARTIALLY DEPLETED SILICON ON INSULATOR TECHNOLOGY; PSEUDOSTATIC CIRCUITS; SENSE AMPLIFIER;

STATIC RANDOM ACCESS STORAGE;

EID: 0242443402     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. D. J. Schepis et al., "A 0.25μm CMOS SOI technology and its application to 4 Mb SRAM", Proc. IEDM, December, 1997, pp. 587-590.
2. R. V. Joshi et al., "A 666 MHz self-resetting 8 Port, 32×64 bits register file and latch in 0.25μm SOI technology", IEEE Int. SOI Conf., October, 1998, pp. 131-132.
3. D. H. Allen et al., "A 0.2μm 1.8 V SOI 550MHz 64 b PowerPC microprocessor with copper interconnects", Proc. ISSCC Conf., October, 1999, 438-439.
4. R. V. Joshi et al., "A 2 GHz cycle, 430 ps access time 34 Kb L1 directory SRAM in 1.5 V, 0.18μm CMOS bulk technology", IEEE 2000 Symp. on VLSI circuits, June, 2000, pp. 222-225.