A 6GHz, 16Kbytes L1 cache in a 100nm dual-VT technology using a bitline leakage reduction (BLR) technique

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 50-51

  Ye, Yibin ^a   Khellah, Muhammad ^a   Somasekhar, Dinesh ^a   Farhang, Ali ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; DESIGN FOR TESTABILITY; NANOTECHNOLOGY; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE;

BITLINE LEAKAGE REDUCTION; CACHE DESIGN;

CACHE MEMORY;

EID: 0242611669     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. K. Itoh et. al., 1996 Symp. VLSI Circuits, pp. 132-133.
2. K. Agawa et. al., 2000 Symp. VLSI Circuits, pp. 70-71.