-
2
-
-
0029539421
-
Manufacturing technology challenges for low power electronics, in
-
Z. J. Lemnios, "Manufacturing technology challenges for low power electronics," in Dig. Tech. Papers, Syitip. VLSI Technology, 1995, pp. 5-8.
-
(1995)
Dig. Tech. Papers, Syitip. VLSI Technology
, pp. 5-8
-
-
Lemnios, Z.J.1
-
3
-
-
0027889411
-
SOI for a 1-Volt CMOS technology and applications to a 512-Kb SRAM with 3.5 ns access time, in
-
G. G. Shahidi et al, "SOI for a 1-Volt CMOS technology and applications to a 512-Kb SRAM with 3.5 ns access time," in IEDM Tech. Dig., 1993, pp. 813-816.
-
(1993)
IEDM Tech. Dig.
, pp. 813-816
-
-
Shahidi, G.G.1
-
4
-
-
0029233869
-
CMOS scaling in the 0.1-/jm, I.X-Volt regime for highperformance applications
-
Jan./Mar.
-
_, "CMOS scaling in the 0.1-/jm, I.X-Volt regime for highperformance applications," IBM J. Res. Develop., vol. 39, no. 1/2, pp. 229-244, Jan./Mar. 1995.
-
(1995)
IBM J. Res. Develop.
, vol.39
, Issue.1-2
, pp. 229-244
-
-
-
5
-
-
0029219539
-
CMOS scaling into the21st century: 0.1 /im and beyond, IBM J
-
JanTMar.
-
Y. Taur et al., "CMOS scaling into the21st century: 0.1 /im and beyond," IBM J. Res. Develop., vol. 39, no. 1/2, pp. 245-260, JanTMar. 1995.
-
(1995)
Res. Develop.
, vol.39
, Issue.1-2
, pp. 245-260
-
-
Taur, Y.1
-
6
-
-
0028743284
-
A room temperature 0.1 /im CMOS on SOI, IEEE Trans
-
Dec.
-
G. G. Shahidi et al., "A room temperature 0.1 /im CMOS on SOI," IEEE Trans. Electron Devices, vol. 41, pp. 2405-2412, Dec. 1994.
-
(1994)
Electron Devices
, vol.41
, pp. 2405-2412
-
-
Shahidi, G.G.1
-
7
-
-
17144449930
-
Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing, in
-
_, "Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing," in IEDM Tech. Dig., 1990, pp. 587-590.
-
(1990)
IEDM Tech. Dig.
, pp. 587-590
-
-
-
8
-
-
0029406028
-
Transient behavior of the kink effect in partially-depleted SOI MOSFET's
-
Nov.
-
A. Wei, M. J. Shcrony, and D. A. Antoniadis, "Transient behavior of the kink effect in partially-depleted SOI MOSFET's," IEEE Electron Device Lett., vol. 16, pp. 494-496, Nov. 1995.
-
(1995)
IEEE Electron Device Lett.
, vol.16
, pp. 494-496
-
-
Wei, A.1
Shcrony, M.J.2
Antoniadis, D.A.3
-
9
-
-
0028735418
-
Dynamic floating-body instabilities in partially depleted SOI CMOS circuits
-
D. Suh and J. G. Possum, "Dynamic floating-body instabilities in partially depleted SOI CMOS circuits," in 1EDM Tech. Dig 1994, pp. 661-664.
-
(1994)
1EDM Tech. Dig
, pp. 661-664
-
-
Suh, D.1
Possum, J.G.2
-
10
-
-
0029546067
-
Low-voltage transient bipolar effect induced by dynamic floating-body charging in PD/SOI MOSFET's, in
-
M. M. Pelella, J. G. Possum, D. Suh, S. Krishnan, and K. A. Jenkins, "Low-voltage transient bipolar effect induced by dynamic floating-body charging in PD/SOI MOSFET's," in Pmc. IEEE Int. SOI Conf., Oct. 1995, pp. 8-9.
-
(1995)
Pmc. IEEE Int. SOI Conf., Oct.
, pp. 8-9
-
-
Pelella, M.M.1
Possum, J.G.2
Suh, D.3
Krishnan, S.4
Jenkins, K.A.5
-
11
-
-
0029409871
-
On the transient operation of partially depleted SOI NMOSFET's
-
Nov.
-
J. Gautier and J. Y. C. Sun, "On the transient operation of partially depleted SOI NMOSFET's," IEEE Electron Device Lett., vol. 16, pp. 497-499, Nov. 1995.
-
(1995)
IEEE Electron Device Lett.
, vol.16
, pp. 497-499
-
-
Gautier, J.1
Sun, J.Y.C.2
-
12
-
-
0029701842
-
Floating body effects in partially-depleted SOI CMOS circuits
-
P. F. Lu, J. Ji, C. T. Chuang, L. F. Wagner, C. M. Hsieh, J. B. Kuang, L. Hsu, M. M. Pelella, S. Chu, and C. J. Anderson, "Floating body effects in partially-depleted SOI CMOS circuits," in Pmc. 1996 Int. Symp. Low Power Electronics and Design, Monterey, CA, Aug. 12-14, 1996, pp. 139-144.
-
(1996)
Pmc. 1996 Int. Symp. Low Power Electronics and Design, Monterey, CA, Aug. 12-14
, pp. 139-144
-
-
Lu, P.F.1
Ji, J.2
Chuang, C.T.3
Wagner, L.F.4
Hsieh, C.M.5
Kuang, J.B.6
Hsu, L.7
Pelella, M.M.8
Chu, S.9
Anderson, C.J.10
-
13
-
-
0030150564
-
Measurement of transient effects in SOI DRAM/SRAM access transistors
-
May
-
A. Wei and D. A. Antoniadis, "Measurement of transient effects in SOI DRAM/SRAM access transistors," IEEE Electron Device Lett., vol. 17, pp.193-195, May 1996.
-
(1996)
IEEE Electron Device Lett.
, vol.17
, pp. 193-195
-
-
Wei, A.1
Antoniadis, D.A.2
-
14
-
-
0030151464
-
Low-voltage transient bipolar effect induced by dynamic floating-body charging in scaled PD/SOI MOSFET's
-
May
-
M. M. Pelella, J. G. Possum, D. Suh, S. Krishnan, K. A. Jenkins, and M. J. Hargrove, "Low-voltage transient bipolar effect induced by dynamic floating-body charging in scaled PD/SOI MOSFET's," IEEE Electron Device Lett., vol. 17, pp.196-198, May 1996.
-
(1996)
IEEE Electron Device Lett.
, vol.17
, pp. 196-198
-
-
Pelella, M.M.1
Possum, J.G.2
Suh, D.3
Krishnan, S.4
Jenkins, K.A.5
Hargrove, M.J.6
-
15
-
-
0031210445
-
Floating body effects in partially-depleted SOI CMOS circuits
-
Aug.
-
P. F. Lu, C. T. Chuang, J. Ji, L. F. Wagner, C. M. Hsieh, J. B. Kuang, L. Hsu, M. M. Pelella, S. Chu, and C. J. Anderson, "Floating body effects in partially-depleted SOI CMOS circuits," IEEE J. Solid-State Circuits, vol. 32, pp. 1241-1253, Aug. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, pp. 1241-1253
-
-
Lu, P.F.1
Chuang, C.T.2
Ji, J.3
Wagner, L.F.4
Hsieh, C.M.5
Kuang, J.B.6
Hsu, L.7
Pelella, M.M.8
Chu, S.9
Anderson, C.J.10
-
16
-
-
0030081725
-
A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 /im CMOS process
-
H. Pilo, S. Lamphicr, F. Towler, and R. Hee, "A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 /im CMOS process," in ISSCCDig. Tech. Papers, 1996, pp. 148-149.
-
(1996)
ISSCCDig. Tech. Papers
, pp. 148-149
-
-
Pilo, H.1
Lamphicr, S.2
Towler, F.3
Hee, R.4
-
17
-
-
0029723442
-
A 2 ns access, 500 MHz 288 Kb SRAM Macro, in
-
A. Pelella, P. F. Lu, Y. Chan, W. Huott, U. Bakhru, S. Kowalczyk, P. Patel, J. Rawlins, and P. Wu, "A 2 ns access, 500 MHz 288 Kb SRAM Macro," in Dig. Tech. Papers, Symp. VLSI Circuits, 1996, pp. 128-129.
-
(1996)
Dig. Tech. Papers, Symp. VLSI Circuits
, pp. 128-129
-
-
Pelella, A.1
Lu, P.F.2
Chan, Y.3
Huott, W.4
Bakhru, U.5
Kowalczyk, S.6
Patel, P.7
Rawlins, J.8
Wu, P.9
-
18
-
-
0019551234
-
A fieldfunneling effect on the collection of alpha-particle-generated carriers in silicon devices
-
Apr.
-
C. M. Hsieh, P. C. Muriey, and R. R. O'Brien, "A fieldfunneling effect on the collection of alpha-particle-generated carriers in silicon devices," IEEE Electron Devices Lett., vol. EDL-2, pp. 104-106, Apr. 1981.
-
(1981)
IEEE Electron Devices Lett.
, vol.EDL-2
, pp. 104-106
-
-
Hsieh, C.M.1
Muriey, P.C.2
O'Brien, R.R.3
-
19
-
-
0024908421
-
Model for CMOS/SOI single-event vulnerability
-
Dec.
-
S. E. Kerns, L. W. Massengill, D. V. Kerns, Jr., M. L. Alles, T. W. Houston, H. Lu, and L. R. Hitc, "Model for CMOS/SOI single-event vulnerability," IEEE Trans. Nucl. Sei., vol. 36, pp. 2305-2310, Dec. 1989.
-
(1989)
IEEE Trans. Nucl. Sei.
, vol.36
, pp. 2305-2310
-
-
Kerns, S.E.1
Massengill, L.W.2
Kerns Jr., D.V.3
Alles, M.L.4
Houston, T.W.5
Lu, H.6
Hitc, L.R.7
-
20
-
-
0026866625
-
Numerical analysis of alpha-particleinduced soft errors in SOI MOS devices
-
May
-
H. Iwata and Ohzone, "Numerical analysis of alpha-particleinduced soft errors in SOI MOS devices," IEEE Trans. Electron Devices, vol. 39, pp. 1184-1190, May 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, pp. 1184-1190
-
-
Iwata, H.1
Ohzone2
-
21
-
-
0029544310
-
-
Y. Tosaka, K. Suzuki, and T. Sugii, 'Vv-particle-induced soft errors in submicron SOI SRAM," in Dig. Tech. Papers, S\inp. VLSI Technology. 1995, pp. 39-40.
-
(1995)
Dig. Tech. Papers, S\inp. VLSI Technology.
, pp. 39-40
-
-
Tosaka, Y.1
Suzuki, K.2
Sugii, T.3
Sram, P.-I.4
-
22
-
-
0031162949
-
SRAM bitline circuits on PD SOI: Advantages and concerns
-
June
-
J. B. Kuang, S. Ratanaphanyarat, M. J. Saccamango, L. Hsu, R. C. Flaker, L. F. Wagner, S. Chu, and G. G. Shahidi, "SRAM bitline circuits on PD SOI: Advantages and concerns," IEEE J. Solid-State Circuits, vol. 32, pp. 837-844, June 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, pp. 837-844
-
-
Kuang, J.B.1
Ratanaphanyarat, S.2
Saccamango, M.J.3
Hsu, L.4
Flaker, R.C.5
Wagner, L.F.6
Chu, S.7
Shahidi, G.G.8
-
24
-
-
0031382797
-
A new SRAM cell design using 0.35 //m CMOS/SIMOX technology, in
-
K. Kumagai, T. Yamada, H. Iwaki, H. Nakamura, and H. Onishi, "A new "SRAM cell design using 0.35 //m CMOS/SIMOX technology," in Pmc. IEEE Int. SOI Conf., 1997, pp. 174-175.
-
(1997)
Pmc. IEEE Int. SOI Conf.
, pp. 174-175
-
-
Kumagai, K.1
Yamada, T.2
Iwaki, H.3
Nakamura, H.4
Onishi, H.5
-
25
-
-
0028124010
-
An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology, in ISSCC Dig
-
K. Suma et al., "An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology," in ISSCC Dig. Tech. Papers. 1994, pp. 138-139.
-
(1994)
Tech. Papers.
, pp. 138-139
-
-
Suma, K.1
-
26
-
-
0029481651
-
Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOIDRAM, in Dig
-
F. Morishita et al., "Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOIDRAM," in Dig. Tech. Papers, S\mp. VLSI Technology; 1995, pp. 141-142.
-
(1995)
Tech. Papers, S\mp. VLSI Technology
, pp. 141-142
-
-
Morishita, F.1
-
27
-
-
0028602215
-
Enhancement of data retention time for giga-bit DRAM's using SIMOX technology, in
-
T. Tanigawa, A. Yoshino, H. Koga, and S. Ohya, "Enhancement of data retention time for giga-bit DRAM's using SIMOX technology," in Dig. Tech. Papers, S\mp. VLSI Technology; 1994, pp. 37-38.
-
(1994)
Dig. Tech. Papers, S\mp. VLSI Technology
, pp. 37-38
-
-
Tanigawa, T.1
Yoshino, A.2
Koga, H.3
Ohya, S.4
-
28
-
-
0029703315
-
A long data retention SOI-DRAM with the body refresh function, in
-
S; Tomishima et al, "A long data retention SOI-DRAM with the body refresh function," in Dig. Tech. Papers, S\mp. VLSI Circuits, 1996, pp.198-199.
-
(1996)
Dig. Tech. Papers, S\mp. VLSI Circuits
, pp. 198-199
-
-
Tomishima, S.1
-
29
-
-
0029482709
-
A high performance 16 M DRAM on a thin film SOI, in
-
H. S. Kini et al.. "A high performance 16 M DRAM on a thin film SOI," in Dig. Tech. Papers. Svmp. VLSI Technology, 1995, pp. 143-144.
-
(1995)
Dig. Tech. Papers. Svmp. VLSI Technology
, pp. 143-144
-
-
Kini, H.S.1
-
30
-
-
0028572694
-
Data retention in ultra-thin-film-SOl DRAM with buried capacitor cell, in
-
T. Nishihara, H. Moriya, N. Ikcda, H. Aozasa, and Y. Miyazawa, "Data retention in ultra-thin-film-SOl DRAM with buried capacitor cell," in Dig. Tech. Papers, S\mp. VLSI Technolog 1994, pp. 39-40.
-
(1994)
Dig. Tech. Papers, S\mp. VLSI Technolog
, pp. 39-40
-
-
Nishihara, T.1
Moriya, H.2
Ikcda, N.3
Aozasa, H.4
Miyazawa, Y.5
-
31
-
-
0028126176
-
A 34 ns 256 Mb DRAM with boosted sense-ground scheme
-
M. Asakura et al., "A 34 ns 256 Mb DRAM with boosted sense-ground scheme," ISSCC Dig. Tech. Papers, 1994, pp. 140-141.
-
(1994)
ISSCC Dig. Tech. Papers
, pp. 140-141
-
-
Asakura, M.1
-
32
-
-
0028538213
-
An experimental 256-Mb DRAM with boosted senseground scheme
-
Nov.
-
_, "An experimental 256-Mb DRAM with boosted senseground scheme," IEEE J. Solid-State Circuits, vol. 29, pp. 1303-1309, Nov. 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, pp. 1303-1309
-
-
-
33
-
-
0028608450
-
An automatic temperature compensation of internal sense ground for sub-quarter micron DRAM's, in
-
T. Ooishi et al., "An automatic temperature compensation of internal sense ground for sub-quarter micron DRAM's," in Dig. Tech. Papers, Symp. VLSI Circuits, 1994, pp. 77-78.
-
(1994)
Dig. Tech. Papers, Symp. VLSI Circuits
, pp. 77-78
-
-
Ooishi, T.1
-
34
-
-
0030385812
-
Analysis of floating-bodyinduced leakage current in 0.15 ;/m SOI DRAM, in
-
M. Terauchi and M. Yoshimi, "Analysis of floating-bodyinduced leakage current in 0.15 ;/m SOI DRAM," in Proc. IEEE Int. SOfConf., 1996, pp. 138-139.
-
(1996)
Proc. IEEE Int. SOfConf.
, pp. 138-139
-
-
Terauchi, M.1
Yoshimi, M.2
-
35
-
-
0028273707
-
Accurate, predictive modeling of soft error rate due to cosmic rays and chip n radiation, in
-
G. R. Srinivanson et al., "Accurate, predictive modeling of soft error rate due to cosmic rays and chip n radiation," in Proc. IRPS, 1994, pp. 12-16.
-
(1994)
Proc. IRPS
, pp. 12-16
-
-
Srinivanson, G.R.1
-
36
-
-
0028705539
-
Single event upset and charge collection measurements during high-energy protons and neutrons
-
E. Normond et al., "Single event upset and charge collection measurements during high-energy protons and neutrons," IEEE Trans. Nncl. Sei., vol. 41, pp. 2203-2209, 1994.
-
(1994)
IEEE Trans. Nncl. Sei.
, vol.41
, pp. 2203-2209
-
-
Normond, E.1
-
37
-
-
0029725242
-
Direct measurement for SOI and bulk diodes of single-event-upset charge collection from energetic ions and alpha particles, in
-
T. Aton et al., "Direct measurement for SOI and bulk diodes of single-event-upset charge collection from energetic ions and alpha particles," in Dig. Tech. Papers, Symp. VLSI Technology, 1996, pp. 98-99.
-
(1996)
Dig. Tech. Papers, Symp. VLSI Technology
, pp. 98-99
-
-
Aton, T.1
-
39
-
-
0030658640
-
Dual-mode parasitic bipolar effect in dynamic CVSL XOR circuit with floating-body partially-depleted SOI devices
-
Taipei, Taiwan, June 3-5
-
C. T. Chuang, P. F. Lu, J. Ji, L. F. Wagner, S. Chu, and C. J. Anderson, "Dual-mode parasitic bipolar effect in dynamic CVSL XOR circuit with floating-body partially-depleted SOI devices," in Proc. Tech. Papers, Int. Symp. VLSI Technology, Systems, and Applications, Taipei, Taiwan, June 3-5, 1997, pp. 288-292.
-
(1997)
Proc. Tech. Papers, Int. Symp. VLSI Technology, Systems, and Applications
, pp. 288-292
-
-
Chuang, C.T.1
Lu, P.F.2
Ji, J.3
Wagner, L.F.4
Chu, S.5
Anderson, C.J.6
-
40
-
-
0030216887
-
Minimizing floatingbody-induced threshold voltage variation in partially depleted SOI CMOS
-
Aua.
-
A. Wei, D. A. Antoniadis, and L. A. Bair, "Minimizing floatingbody-induced threshold voltage variation in partially depleted SOI CMOS," IEEE Electron Device Lett., vol. 17, pp. 391-394, Aua. 1996.
-
(1996)
IEEE Electron Device Lett.
, vol.17
, pp. 391-394
-
-
Wei, A.1
Antoniadis, D.A.2
Bair, L.A.3
-
41
-
-
4243098401
-
A 2 ns cycle, 4 ns access 512 kb CMOS ECL SRAM
-
T. I. Chappell, B. A. Chappell, S. E. Schuster, J. W. Allan, S. P. Klepner, R. V. Joshi, and R. L. Franch, "A 2 ns cycle, 4 ns access 512 kb CMOS ECL SRAM," ISSCC Dig. Tech. Papers, 1991, pp. 50-51.
-
(1991)
ISSCC Dig. Tech. Papers
, pp. 50-51
-
-
Chappell, T.I.1
Chappell, B.A.2
Schuster, S.E.3
Allan, J.W.4
Klepner, S.P.5
Joshi, R.V.6
Franch, R.L.7
-
42
-
-
0025419522
-
A 3.8-ns CMOS 16 x 16-b multiplier using complementary pass-transistor logic
-
Mar.
-
K. Yano et al., "A 3.8-ns CMOS 16 x 16-b multiplier using complementary pass-transistor logic," IEEE J. Solid-State Circuits, vol. 25, pp. 388-395, Mar. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 388-395
-
-
Yano, K.1
-
43
-
-
85060884542
-
A 1.5 ns 32 b CMOS ALU in double pass-transistor logic, in
-
M. Suzuki el at., "A 1.5 ns 32 b CMOS ALU in double pass-transistor logic," in ISSCC Dig. Tech. Papers, 1993, pp. 90-91.
-
(1993)
ISSCC Dig. Tech. Papers
, pp. 90-91
-
-
Suzuki, M.1
-
44
-
-
0029532072
-
Multi-level pass-transistor logic for low-power ULSI, in
-
Y. Sasaki, K. Yano, S. Yamashita, and H. Chikata, "Multi-level pass-transistor logic for low-power ULSI," in Dig. Tech. Papers, S\mp. Low Power Electronics, 1995, pp. 14-17.
-
(1995)
Dig. Tech. Papers, S\mp. Low Power Electronics
, pp. 14-17
-
-
Sasaki, Y.1
Yano, K.2
Yamashita, S.3
Chikata, H.4
-
45
-
-
0028745562
-
A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation, in
-
F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu, "A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation," in IEDM Tech. Dig., 1994, pp. 809-812.
-
(1994)
IEDM Tech. Dig.
, pp. 809-812
-
-
Assaderaghi, F.1
Sinitsky, D.2
Parke, S.3
Bokor, J.4
Ko, P.K.5
Hu, C.6
-
46
-
-
0029544885
-
SOI-DRAM circuit technologie, for low power high speed multi-giga scale memories, in
-
S. Kuge, T. Tsuruda, S. Tomishima, M. Tsukude, T. Yamagata, and K. Arimoto, "SOI-DRAM circuit technologie, for low power high speed multi-giga scale memories," in Dig. Tech. Papers, Symp. VLSI Circuits, 1995, pp. 103-104.
-
(1995)
Dig. Tech. Papers, Symp. VLSI Circuits
, pp. 103-104
-
-
Kuge, S.1
Tsuruda, T.2
Tomishima, S.3
Tsukude, M.4
Yamagata, T.5
Arimoto, K.6
-
47
-
-
0031069028
-
A 1 V 46 ns 16 Mb SOI-DRAM with body control technique
-
K. Shimomura et al., "A 1 V 46 ns 16 Mb SOI-DRAM with body control technique," ISSCC Dig. Tech. Papers, 1997, pp. 68-69.
-
(1997)
ISSCC Dig. Tech. Papers
, pp. 68-69
-
-
Shimomura, K.1
-
48
-
-
85051964495
-
1-V high-speed digital circuit technology with 0.5 /im multi-threshold CMOS, in
-
S. Mutoh et cil., "1-V high-speed digital circuit technology with 0.5 /im multi-threshold CMOS," in Proc. IEEE Int. ASIC Conf., 1993, pp. 186-189.
-
(1993)
Proc. IEEE Int. ASIC Conf.
, pp. 186-189
-
-
Mutoh, S.1
-
49
-
-
0030085998
-
A 0.5 V SIMOX-MTCMOS circuit with 200 ps logic gate, in
-
T. Douseki, S. Shigematsu, Y. Tanabe, M. Harada, H. Inokawa, and T. Tsuchiya, "A 0.5 V SIMOX-MTCMOS circuit with 200 ps logic gate," in ISSCC Dig. Tech. Papers, 1996, pp. 84-85.
-
(1996)
ISSCC Dig. Tech. Papers
, pp. 84-85
-
-
Douseki, T.1
Shigematsu, S.2
Tanabe, Y.3
Harada, M.4
Inokawa, H.5
Tsuchiya, T.6
-
50
-
-
0030087134
-
0.5 V SOI CMOS pass-gate logic
-
T. Fuse, Y. Oowaki, M. Terauchi, S. Watanabe, M. Yoshimi, K. Ohuchi, and J. Matsunaga, "0.5 V SOI CMOS pass-gate logic," in ISSCC Dig. Tech. Papers. 1996, pp. 88-89.
-
(1996)
ISSCC Dig. Tech. Papers.
, pp. 88-89
-
-
Fuse, T.1
Oowaki, Y.2
Terauchi, M.3
Watanabe, S.4
Yoshimi, M.5
Ohuchi, K.6
Matsunaga, J.7
-
51
-
-
0031073501
-
A 0.5 V 200 MHz 1-stage 32b ALU using a body bias controlled SOI pass-gate logic, in
-
T. Fuse et al., "A 0.5 V 200 MHz 1-stage 32b ALU using a body bias controlled SOI pass-gate logic," in ISSCC Dig. Tech. Papers, 1997, pp. 286-287.
-
(1997)
ISSCC Dig. Tech. Papers
, pp. 286-287
-
-
Fuse, T.1
-
52
-
-
0031071448
-
A l V CMOS digital circuit with double:gate-driven MOSFET, in
-
L. S. Y. Wong and G. A. Rigby, "A l V CMOS digital circuit with double:gate-driven MOSFET," in ISSCC Dig. Tech. Papers, 1997, pp. 292-293.
-
(1997)
ISSCC Dig. Tech. Papers
, pp. 292-293
-
-
Wong, L.S.Y.1
Rigby, G.A.2
-
53
-
-
0031356848
-
Active body-bias SOI-CMOS driver circuits, in
-
Y. Wada et al., "Active body-bias SOI-CMOS driver circuits," in Dis- Tech. Papers, Svnip. VLSI Circuits, 1997, pp. 29-30.
-
(1997)
Dis- Tech. Papers, Svnip. VLSI Circuits
, pp. 29-30
-
-
Wada, Y.1
-
54
-
-
0030394559
-
A new SOI inverter for low power applications, in
-
I. Y. Chung, Y. J. Park, and H. S. Min, "A new SOI inverter for low power applications," in Proc. IEEE Int. SOI Conf., 1996, pp. 20-21.
-
(1996)
Proc. IEEE Int. SOI Conf.
, pp. 20-21
-
-
Chung, I.Y.1
Park, Y.J.2
Min, H.S.3
-
55
-
-
0031377797
-
High speed SOI buffer circuit with the efficient connection of subsidiary MOSFET's for dynamic threshold control, in
-
J. H. Lee and Y. J. Park, "High speed SOI buffer circuit with the efficient connection of subsidiary MOSFET's for dynamic threshold control," in Proc. IEEE Int. SOI Conf., 1997, pp. 152-153.
-
(1997)
Proc. IEEE Int. SOI Conf.
, pp. 152-153
-
-
Lee, J.H.1
Park, Y.J.2
-
56
-
-
0031362883
-
A novel dynamic Vi circuit configuration, in
-
T. W. Houston, "A novel dynamic Vi circuit configuration," in Proc. IEEE Int. SOI Conf., 1997, pp. 154-155.
-
(1997)
Proc. IEEE Int. SOI Conf.
, pp. 154-155
-
-
Houston, T.W.1
-
57
-
-
0031074275
-
A CAO-compatible SOI/CMOS gate array having body-fixed partially-depleted transistors, in
-
K. Ueda et al, "A CAO-compatible SOI/CMOS gate array having body-fixed partially-depleted transistors," in ISCC Dig. Tech. Papers, 1997, pp. 288-289.
-
(1997)
ISCC Dig. Tech. Papers
, pp. 288-289
-
-
Ueda, K.1
-
58
-
-
0030080141
-
High-speed SOI 1/8 frequency divider using field-shield body-fixed structure
-
T. Iwamatsu etal., "High-speed SOI 1/8 frequency divider using field-shield body-fixed structure," Jpn. J. Appl. Phvs., vol. 35, pp. 965-968, 1996.
-
(1996)
Jpn. J. Appl. Phvs.
, vol.35
, pp. 965-968
-
-
Iwamatsu, T.1
-
59
-
-
33747946662
-
A 200MHz 64b dual-issue CMOS microprocessor, in
-
D. Dobberpuhl et al., "A 200MHz 64b dual-issue CMOS microprocessor," in ISCC Dig. Tech. Papers, 1992, pp. 106-107.
-
(1992)
ISCC Dig. Tech. Papers
, pp. 106-107
-
-
Dobberpuhl, D.1
-
60
-
-
0026955423
-
A 200-MHz 64-b dual-issue CMOS microprocessor
-
Nov.
-
_, "A 200-MHz 64-b dual-issue CMOS microprocessor," IEEEJ. Solid-State Circuits, vol. 27, pp. 1555-1567, Nov. 1992.
-
(1992)
IEEEJ. Solid-State Circuits
, vol.27
, pp. 1555-1567
-
-
-
61
-
-
0030085953
-
A 433 MHz 64 b quad-issue RISC microprocessor, in
-
P. E. Gronowski et al., "A 433 MHz 64 b quad-issue RISC microprocessor," in ISSCCDig. Tech. Papers, 1996, pp. 222-223.
-
(1996)
ISSCCDig. Tech. Papers
, pp. 222-223
-
-
Gronowski, P.E.1
-
62
-
-
0031335848
-
Efficacy of body ties under dynamic switching conditions in partially-depleted SOI CMOS technology, in
-
S. Krishnan, "Efficacy of body ties under dynamic switching conditions in partially-depleted SOI CMOS technology," in Proc. IEEE Int. SOI Conf., 1997, pp. 140-141.
-
(1997)
Proc. IEEE Int. SOI Conf.
, pp. 140-141
-
-
Krishnan, S.1
-
63
-
-
11644262536
-
A compact Schottky contact technology for SOI transistors
-
J. Sleight and K. Mistry, "A compact Schottky contact technology" for SOI transistors," in IEDM Tech. Dig., 1997, pp. 419-422.
-
(1997)
IEDM Tech. Dig.
, pp. 419-422
-
-
Sleight, J.1
Mistry, K.2
-
64
-
-
0041958944
-
A 2.0 V, 0.35 /im partially depleted SOI-CMOS technology, in
-
K. Mistry, G. Grula, J. Sleight, L. Bair, R. Stephany, R. Flatley, and P. Skerry, "A 2.0 V, 0.35 /im partially depleted SOI-CMOS technology," in IEDM Tech. Dig., 1997, pp. 583-586.
-
(1997)
IEDM Tech. Dig.
, pp. 583-586
-
-
Mistry, K.1
Grula, G.2
Sleight, J.3
Bair, L.4
Stephany, R.5
Flatley, R.6
Skerry, P.7
-
65
-
-
84886448032
-
1 giga bit SOI DRAM with fully bulk compatible process and body-contacted SOI MOSFET structure, in
-
Y. H. Koh et al., "1 giga bit SOI DRAM with fully bulk compatible process and body-contacted SOI MOSFET structure," in IEDM Tech. Dig., 1997, pp. 579-582.
-
(1997)
IEDM Tech. Dig.
, pp. 579-582
-
-
Koh, Y.H.1
-
66
-
-
0008017831
-
Analysis of snapback in SOI NMOSFET's and its use for an SOI ESD protection circuit, in
-
K. Vcrhaege, G. Groeseneken, J. P. Colinge, and H. E. Macs, "Analysis of snapback in SOI NMOSFET's and its use for an SOI ESD protection circuit," in P roc. IEEE Int. SOI Conf., 1992, pp. 140-141.
-
(1992)
P Roc. IEEE Int. SOI Conf.
, pp. 140-141
-
-
Vcrhaege, K.1
Groeseneken, G.2
Colinge, J.P.3
Macs, H.E.4
-
67
-
-
0027628980
-
Double snapback in SOI NMOSFET's and its application for SOI ESD protection
-
July
-
_, "Double snapback in SOI NMOSFET's and its application for SOI ESD protection," IEEE Electron Device Lett., vol. 14, pp. 326-328, July 1993.
-
(1993)
IEEE Electron Device Lett.
, vol.14
, pp. 326-328
-
-
-
68
-
-
0029394387
-
ESD reliability and protection schemes in SOI CMOS output buffers
-
Oct.
-
M. Chan, S. S. Yuen, Z. J. Ma, K. Y. Hui, P. K. Ko, and C. Hu, "ESD reliability and protection schemes in SOI CMOS output buffers," IEEE Trans. Electron Devices, vol. 42, pp. 1816-1821, Oct. 1995.
-
(1995)
IEEE Trans. Electron Devices
, vol.42
, pp. 1816-1821
-
-
Chan, M.1
Yuen, S.S.2
Ma, Z.J.3
Hui, K.Y.4
Ko, P.K.5
Hu, C.6
-
69
-
-
0029720019
-
ESD design for deep submicron SOI technology, in
-
C. Duvvury, A. Amerasekera, K. Joyner, S. Ramaswamy, and S. Young, "ESD design for deep submicron SOI technology," in Dig. Tech. Papers, Symp. VLSI Technology, 1996, pp.194-195.
-
(1996)
Dig. Tech. Papers, Symp. VLSI Technology
, pp. 194-195
-
-
Duvvury, C.1
Amerasekera, A.2
Joyner, K.3
Ramaswamy, S.4
Young, S.5
-
70
-
-
0030410190
-
An ESD protection circuit for TFSOI technology, in
-
J. C. Smith, M. Lien, and S. Veeraraghavan, "An ESD protection circuit for TFSOI technology," in Proc. IEEE Int. SOI Conf.. 1996, pp. 170-171.
-
(1996)
Proc. IEEE Int. SOI Conf.
, pp. 170-171
-
-
Smith, J.C.1
Lien, M.2
Veeraraghavan, S.3
-
71
-
-
0024680209
-
Physical origin of the negative differential resistance in SOI transistors
-
June 22
-
L. J. McDaid, S. Hall, P. H. Mellor, W. Ecclcston, and J. C. Alderman, "Physical origin of the negative differential resistance in SOI transistors," Electron. Lett., vol. 25, no. 13, pp. 827-828, June 22, 1989.
-
(1989)
Electron. Lett.
, vol.25
, Issue.13
, pp. 827-828
-
-
McDaid, L.J.1
Hall, S.2
Mellor, P.H.3
Ecclcston, W.4
Alderman, J.C.5
-
72
-
-
84939377322
-
Effect of microscale thermal conduction on the packing limit of silicon-on-insulator electronic devices
-
Oct.
-
K. E. Goodson and M. I. Flik, "Effect of microscale thermal conduction on the packing limit of silicon-on-insulator electronic devices," IEEE Trans. Coinp., fl\bricls, Maniifact. Techno!., vol. 15, pp. 715-722, Oct. 1992.
-
(1992)
IEEE Trans. Coinp., Fl\bricls, Maniifact. Techno!.
, vol.15
, pp. 715-722
-
-
Goodson, K.E.1
Flik, M.I.2
-
73
-
-
84944378006
-
Measurement and modeling of self-heating in SOI NMOSFET's
-
Jan.
-
L. T. Su, J. E. Chung, D. A. Antoniadis, K. E. Goodson, and M. I. Flik, "Measurement and modeling of self-heating in SOI NMOSFET's," IEEE Trans. Electron Devices, vol. 41, pp. 69-75, Jan. 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, pp. 69-75
-
-
Su, L.T.1
Chung, J.E.2
Antoniadis, D.A.3
Goodson, K.E.4
Flik, M.I.5
-
74
-
-
0029291056
-
Measurement of 1-V curves of silicon-on-insulator (SOI) MOSFET's without self-healing
-
Apr.
-
K. A. Jenkins and J. Y. C. Sun, "Measurement of 1-V curves of silicon-on-insulator (SOI) MOSFET's without self-healing," IEEE Electron Device Lett., vol. 16, pp. 145-147, Apr. 1995.
-
(1995)
IEEE Electron Device Lett.
, vol.16
, pp. 145-147
-
-
Jenkins, K.A.1
Sun, J.Y.C.2
-
75
-
-
84886448134
-
A 0.25 /im CMOS SOI technology and its application to 4 Mb SRAM, in
-
D. J. Schepis et al., "A 0.25 /im CMOS SOI technology and its application to 4 Mb SRAM," in IEDM Tech. Dig., 1997, pp. 587-590.
-
(1997)
IEDM Tech. Dig.
, pp. 587-590
-
-
Schepis, D.J.1
-
76
-
-
84886448057
-
A 7.9/5.5 psec room/low temperature SOI CMOS, in
-
F. Assaderaghi et al., "A 7.9/5.5 psec room/low temperature SOI CMOS," in IEDM Tech. Dig., 1997, pp. 415-418.
-
(1997)
IEDM Tech. Dig.
, pp. 415-418
-
-
Assaderaghi, F.1
-
77
-
-
0030414086
-
Accurate measurement of pass-transistor leakage current in SOI MOSFET's
-
_, "Accurate measurement of pass-transistor leakage current in SOI MOSFET's," in Proc. IEEE Int. SOI Conf., 1996, pp. 66-67.
-
(1996)
Proc. IEEE Int. SOI Conf.
, pp. 66-67
-
-
-
78
-
-
84886448111
-
Scalability of partially depleted SOI technology for sub-0.25 /un logic applications, in
-
R. Chau et al., "Scalability of partially depleted SOI technology for sub-0.25 /un logic applications," in IEDM Tech. Dig., 1997, pp. 591-594.
-
(1997)
IEDM Tech. Dig.
, pp. 591-594
-
-
Chau, R.1
-
79
-
-
84886448119
-
Design methodology for minimizing hystcretic I'j-variation in partially-depleted SOI CMOS, in
-
A. Wei and D. Antoniadis, "Design methodology for minimizing hystcretic I'j-variation in partially-depleted SOI CMOS," in 1EDM Tech. Dig., 1997, pp. 411-14.
-
(1997)
1EDM Tech. Dig.
, pp. 411-414
-
-
Wei, A.1
Antoniadis, D.2
|