Novel powering-down scheme for low Vt CMOS circuits

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1998, Pages 44-47

  Kumagai, Kouichi ^a   Iwaki, Hiroaki ^a   Yoshida, Hiroshi ^a   Suzuki, Hisamitsu ^a   Yamada, Takashi ^a   Kurosawa, Susumu ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENT CONTROL; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS;

VIRTUAL POWER/GROUND RAILS CLAMP (VRC) CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0031641123     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)