Power-constrained CMOS scaling limits

IBM Journal of Research and Development

Volumn 46, Issue 2-3, 2002, Pages 235-244

  Frank, David J ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TUNNELING; ENERGY DISSIPATION; FORMAL LOGIC; LEAKAGE CURRENTS; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; VLSI CIRCUITS;

QUANTUM TUNNELING;

CMOS INTEGRATED CIRCUITS;

EID: 0036508274     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.462.0235     Document Type: Article

References (25)

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21. Trading speed for low power by choice of supply and threshold voltages
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23. Supply and threshold voltage optimization for low power design
24. Sub-20 nm CMOS FinFET technologies
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