Leakage scaling in deep submicron CMOS for SoC

IEEE Transactions on Electron Devices

Volumn 49, Issue 6, 2002, Pages 1034-1041

  Lin, Yo Sheng ^a,b,c   Wu, Chung Cheng ^b   Chang, Chih Sheng ^b   Yang, Rong Ping ^b   Chen, Wei Ming ^b   Liaw, Jhon Jhy ^b   Diaz, Carlos H ^a,b  

^a IEEE   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^c NATIONAL CHI NAN UNIVERSITY   (Taiwan)

Author keywords

Deep submicron CMOS; Leakage scaling; Temperature dependence

Indexed keywords

LEAKAGE SCALING;

LEAKAGE CURRENTS; PERMITTIVITY; SEMICONDUCTOR DOPING; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0036611472     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.1003727     Document Type: Article

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