18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 11, 1999, Pages 1492-1500

  Mizuno, Hiroyuki ^a   Ishibashi, Koichiro ^a   Shimura, Takanori ^a   Hattori, Toshihiro ^a   Narita, Susumu ^a   Shiozawa, Kenji ^a   Ikeda, Shuji ^a   Uchiyama, Kunio ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC BATTERIES; ELECTRIC IMPEDANCE; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; SEMICONDUCTOR JUNCTIONS; SUBSTRATES;

STANDBY CURRENTS; SUBTHRESHOLD LEAKAGE CURRENTS; SWITCHED SUBSTRATE-IMPEDANCE SCHEMES;

MICROPROCESSOR CHIPS;

EID: 0033221245     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.799853     Document Type: Article

References (11)

1. O. Nishii, F. Arakawa, K. Ishibashi, S. Nakano, T. Shimura, K. Suzuki, M. Tachibana, Y. Totsuka, T. Tsunoda, K. Uchiyama, T. Yamada, T. Harrori, H. Maejima, N. Nakagawa, S. Narita, M. Seki, Y. Shimazaki, R. Satomura, T. Takasuga, and A. Hasegawa, "A 200 MHz 1.2 W 1.4GFLOPS microprocessor with graphic operation unit," in 1998 Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1998, pp. 288-289.
2. T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, "The impact of gate-induced drain leakage current on MOSFET scaling," in 1987 Int. Electron Device Meeting (IEDM) Tech. Dig., Dec. 1987, pp. 718-721.
3. T. Sakata, M. Horiguchi, and K. Itoh, "Subthreshold-current reduction circuits for multi-Gigabit DRAM's," in 1993 Symp. VLSI Circuits Dig. Tech. Papers, May 1993, pp. 45-46.
4. M. Horiguchi, T. Sakata, and K. Itoh, "Switched-source-impedance CMOS circuit for low standby subthreshold current Giga-scale LSI's," in 1993 Symp. VLSI Circuits Dig. Tech. Papers, May 1993, pp. 47-48.
5. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, and J. Yamada, "1 V high-speed digital circuit technology with 0.5 μm multi-threshold CMOS," in Proc. 6th Annu. IEEE Int. ASIC Conf. Exhibit, 1993, pp. 186-189.
6. 2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme," in 1996 Int. Solid-State Circuit Conf. (ISSCC) Dig. Tech. Papers, Feb. 1996, pp. 166-167.
7. F. Arakawa, "SH4 RISC microprocessor for multimedia," in Proc. Hot Chips IX, Aug. 1997, pp. 165-176.
8. H. Mizuno, K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S. Ikeda, and K. Uchiyama, "A 18-μA-standby-current 1-8-V 200-MHz microprocessor with self substrate-biased data retention mode," in 1999 Int. Solid-State Circuit Conf. (ISSCC) Dig. Tech. Papers, Feb. 1999, pp. 280-281.
9. T. Kuroda, T. Fujita, S. Mita, T. Mori, K. Matsuo, M. Kakumu, and T. Sakurai, "Substrate noise influence on circuit performance in variable threshold-voltage scheme," in Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 1996, pp. 309-312.
10. T CMOS," in 1997 Symp. VLSI Circuits, June 1997, pp. 95-96.
11. G. G. Shahidi, A. Ajmera, F. Assaderaghi, R. J. Bolam, E. Leobandung, W. Rausch, D. Sankus, D. Schepis, L. F. Wagner, K. Wu, and B. Davari, "Partially-depleted SOI technology for digital logic," in 1999 Int. Solid-State Circuit Conf. (ISSCC) Dig. Tech. Papers, Feb. 1999, pp. 426-427.