High soft-error tolerance body-tied SOI technology with partial trench isolation (PTI) for next generation devices

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2002, Pages 48-49

  Hirano, Yuuichi ^a   Iwamatsu, Toshiaki ^a   Shiga, Katsuya ^a   Nii, Kouji ^a   Sonoda, Kenichiro ^a   Matsumoto, Takuji ^a   Maeda, Shigenobu ^a   Yamaguchi, Yasuo ^a   Ipposhi, Takashi ^a   Maegawa, Shigeto ^a   Inoue, Yasuo ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE; ELECTRONS; ERROR ANALYSIS; MOSFET DEVICES; STATIC RANDOM ACCESS STORAGE;

PARTIAL TRENCH ISOLATION (PTI);

SILICON ON INSULATOR TECHNOLOGY;

EID: 0036047590     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)