Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 275-278

  Miyake, T ^a   Yamashita, T ^a   Asari, N ^a   Sekisaka, H ^a   Sakai, T ^a   Matsuura, K ^a   Wakahara, A ^a   Takahashi, H ^a   Hiyama, T ^a   Miyamoto, K ^a   Mori, K ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC FREQUENCY MEASUREMENT; ELECTRIC POWER SUPPLIES TO APPARATUS; MICROPROCESSOR CHIPS; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

BACK BIAS CONTROL; ULTRA LOW THRESHOLD VOLTAGE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034833289     PISSN: 08865930     EISSN: None     Source Type: Journal    
DOI: 10.1109/CICC.2001.929773     Document Type: Article

References (4)

1. A new optimization strategy for CMOS device process in the era of 0.2um and beyond for MPU's and ASIC's
2. Current signatures: Application
3. IDDQ testing in deep submicron integrated circuits