256 Mb SDRAM with subthreshold leakage current suppression

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 80-81,-418

  Hasegawa, Masatoshi ^a   Nakamura, Masayuki ^a   Narui, Seiji ^a   Ohkuma, Sadayuki ^a   Kawase, Yasushi ^a   Endoh, Hitoshi ^a   Miyatake, Shinichi ^a   Akiba, Takesada ^a   Kawakita, Keizo ^a   Yoshida, Makoto ^a   Yamada, Satoru ^a   Sekiguchi, Toshihiro ^a   Asano, Isamu ^a   Tadaki, Yoshitaka ^a   Nagai, Ryo ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; ELECTRIC CURRENT CONTROL; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MOSFET DEVICES; TIMING CIRCUITS;

DELAY LOCKED LOOP (DLL); SUBTHRESHOLD LEAKAGE CURRENT SUPPRESSION SYSTEM (SCSS); SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM);

RANDOM ACCESS STORAGE;

EID: 0031678266     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)