New standby-current reduction technique for deep sub-micron VLSI CMOS circuits: Smart series switch

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 663-666

  Van Der Meer, P R ^a   Van Staveren, A ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CONVENTIONAL METHODS; DEEP SUB-MICRON PROCESS; REDUCTION TECHNIQUES; RING OSCILLATOR; SERIES SWITCHES; STATE INFORMATION; SUB-THRESHOLD CURRENT; SUB-THRESHOLD LEAKAGE CURRENTS;

CMOS INTEGRATED CIRCUITS; OSCILLATORS (ELECTRONIC); SHIFT REGISTERS;

FLIP FLOP CIRCUITS;

EID: 0346715577     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. P.R. van der Meer et al. Ultra-low standby-currents for deep sub-micron vlsi cmos circuits: Smart series switch. ISCAS, 4:1-4, May 2000.
2. S. Shigematsu et al. A 1 V high-speed MTCMOS circuit scheme for power-down application circuits. IEEE Journal of Solid-State Circuits, 32(6):861-869, June 1997.
3. T. Kuroda et al. A 0.9 V, 150 MHz, 10 mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage scheme. IEEE Journal of Solid-State Circuits, 31(11):1770-1777, November 1996.
4. Y. Oowaki et al. A sub-0.1 m circuit design with substrateover-biasing. ISSCC Digest of Technical papers, pages 88-89, February 1998.
5. A. Montree et al. Limitations to adaptive back-bias approach for standby power reduction in deep submicron cmos. Proceedings of the ESSDERC, 1999.