A 4Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 378-379+467

  Yoon, H ^a   Jae Yoon Sim, ^a   Hyun Suk Lee, ^a   Kyu Nam Lim, ^a   Jae Young Lee, ^a   Nam Jong Kim, ^a   Keum Yong Kim, ^a   Sang Man Byun, ^a   Won Suk Yang, ^a   Chang Hyun Choi, ^a   Hong Sik Jeong, ^a   Jei Hwan Yoo, ^a   Seo II, D ^a   Kim, K ^a   Ryu II, B ^a   Chang Gyu Hwang, ^a  

^a Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; GAIN CONTROL; SPURIOUS SIGNAL NOISE;

LATCH AMPLIFIERS; REFERENCE BITLINE CALIBRATION (RBC) SCHEMES; TWISTED OPEN BITLINE (TOB) ARCHITECTURE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0035054940     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A 30-ns 64-Mb DRAM with built-in self-test and self-repair function
2. Twisted bit-line architectures for multi-megabit DRAMs
3. A 1.2V to 1.3V wide-voltage-range DRAM with 0.8V array operation
4. Low-voltage, high-speed circuit design for gigabit DRAM's