-
1
-
-
0029288557
-
Trends in low-power RAM circuit technologies
-
K. Itoh et al., “Trends in low-power RAM circuit technologies,” IEEE Proc., vol. 83, no. 4, Apr. 1995, pp. 524-543.
-
(1995)
IEEE Proc.
, vol.83
, Issue.4
, pp. 524-543
-
-
Itoh, K.1
-
2
-
-
0000318769
-
Low power memory design
-
J. M. Rabaey and M. Pedram, editors, Kluwer Academic Publishers
-
K. Itoh, “Low power memory design,” Low Power Design Methodologies, J. M. Rabaey and M. Pedram, editors, Kluwer Academic Publishers, Oct. 1995, pp. 201-251.
-
(1995)
Low Power Design Methodologies
, pp. 201-251
-
-
Itoh, K.1
-
3
-
-
0029715043
-
Limitations and challenges of multi-gigabit DRAM circuits
-
K. Itoh et al., “Limitations and challenges of multi-gigabit DRAM circuits,” in Symp. VLSI Circ. Dig. Tech. Papers, June 1996, pp. 2-7.
-
(1996)
Symp. VLSI Circ. Dig. Tech. Papers
, pp. 2-7
-
-
Itoh, K.1
-
4
-
-
0025449455
-
Trends in megabit DRAM circuit design
-
K. Itoh, “Trends in megabit DRAM circuit design,” IEEE J. Solid-State Circuits, voi. 25, no. 3, June 1990, pp. 778-789.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, Issue.3
, pp. 778-789
-
-
Itoh, K.1
-
5
-
-
0029666645
-
Missing the memory wall: The case for processor/memory integration
-
A. Saulsbury et al., “Missing the memory wall: the case for processor/memory integration,” 23rd Int. Symp. Computer Architecture, June 1996.
-
(1996)
23Rd Int. Symp. Computer Architecture
-
-
Saulsbury, A.1
-
6
-
-
0028416570
-
Standby/active mode logic for sub-l-V operating ULSI Memory
-
D. Takashima et al., “Standby/active mode logic for sub-l-V operating ULSI Memory,” IEEEJ. Solid-State Circuits, voi. 29, no. 4, April 1994, pp. 441-447.
-
(1994)
IEEEJ. Solid-State Circuits
, vol.29
, Issue.4
, pp. 441-447
-
-
Takashima, D.1
-
7
-
-
0027693918
-
A single-bit line cross-point cell activation (SCPA) architecture for ultra-low-power SRAMs,”
-
M. Ukita et al., “A single-bit line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM’s,” IEEE J. Solid-State Circuits, voi. 28, no. 11, Nov. 1993, pp. 1114-1118.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, Issue.11
, pp. 1114-1118
-
-
Ukita, M.1
-
8
-
-
11744338353
-
A 1-V TFT-load SRAM using a two-step word-voltage method
-
K. Ishibashi et al., “A 1-V TFT-load SRAM using a two-step word-voltage method,” ISSCC Dig. Tech. Papers, Feb. 1992, pp. 206-207.
-
(1992)
ISSCC Dig. Tech. Papers
, pp. 206-207
-
-
Ishibashi, K.1
-
9
-
-
0029292924
-
A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers
-
K. Ishibashi et al., “A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers,” IEEE J. Solid-State Cirsuits, voi. 30, no. 4, Apr. 1995, pp. 480-486.
-
(1995)
IEEE J. Solid-State Cirsuits
, vol.30
, Issue.4
, pp. 480-486
-
-
Ishibashi, K.1
-
11
-
-
0029513481
-
Driving source-line (DSL) cell architecture for sub-l-V high-speed low-power applications
-
H. Mizuno et al., “Driving source-line (DSL) cell architecture for sub-l-V high-speed low-power applications,” Symp. VLSI Circ. Dig. Tech. Papers, Jun. 1995, pp. 25-26.
-
(1995)
Symp. VLSI Circ. Dig. Tech. Papers
, pp. 25-26
-
-
Mizuno, H.1
-
12
-
-
0029723245
-
A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme
-
H. Yamauchi et al., “A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme,” Symp. VLSI Circ. Dig. Tech. Papers, Jun. 1996, pp. 126-127.
-
(1996)
Symp. VLSI Circ. Dig. Tech. Papers
, pp. 126-127
-
-
Yamauchi, H.1
-
13
-
-
0029702076
-
A deep sub-V, single power-supply SRAM cell with multi-VT, boosted storage node and dynamic load
-
T, boosted storage node and dynamic load,” Symp. VLSI Circ. Dig. Tech. Papers, Jun. 1996, pp. 132-133.
-
(1996)
Symp. VLSI Circ. Dig. Tech. Papers
, pp. 132-133
-
-
Itoh, K.1
-
14
-
-
0028755810
-
Techniques to reduce power in fast wide memories
-
B. S. Amruturet et al., “Techniques to reduce power in fast wide memories,” Symp. Low Power Electronics, Oct. 1994, pp. 92-93.
-
(1994)
Symp. Low Power Electronics
, pp. 92-93
-
-
Amruturet, B.S.1
-
15
-
-
0030122630
-
SOI-DRAM circuit technologies for low power high speed multigiga scale memories
-
S. Kuge et al., “SOI-DRAM circuit technologies for low power high speed multigiga scale memories,” IEEE J. Solid-State Circuits, voi. 31, no. 4, Apr. 1995, pp. 586-591.
-
(1995)
IEEE J. Solid-State Circuits
, vol.31
, Issue.4
, pp. 586-591
-
-
Kuge, S.1
-
16
-
-
0029485402
-
A 2-ns, 5-mW, synchronous-powered static-circuit fully associative TLB
-
H. Higuchi et al., “A 2-ns, 5-mW, synchronous-powered static-circuit fully associative TLB,” Symp. VLSI Circ. Dig. Tech. Papers, Jun. 1995, pp. 21-22.
-
(1995)
Symp. VLSI Circ. Dig. Tech. Papers
, pp. 21-22
-
-
Higuchi, H.1
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