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Volumn , Issue , 1998, Pages 313-317

Reviews and prospects of low-power memory circuits

(1)  Itoh, Kiyoo a  

a NONE

Author keywords

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Indexed keywords


EID: 84928236510     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1109/9780470545058.part6     Document Type: Chapter
Times cited : (4)

References (16)
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  • 2
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  • 3
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  • 6
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  • 7
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  • 8
    • 11744338353 scopus 로고
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  • 9
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  • 12
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    • H. Yamauchi et al., “A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme,” Symp. VLSI Circ. Dig. Tech. Papers, Jun. 1996, pp. 126-127.
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  • 13
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  • 15
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.