|
|
|
Volumn , Issue , 2001, Pages 429-432
|
|
FD/DG-SOI MOSFET - a viable approach to overcoming the device scaling limit
a
a
HITACHI LTD
(Japan)
|
|
Author keywords
[No Author keywords available]
|
|
Indexed keywords
CMOS INTEGRATED CIRCUITS;
ELECTRIC RESISTANCE MEASUREMENT;
MICROELECTRONIC PROCESSING;
SEMICONDUCTOR DEVICE STRUCTURES;
SEMICONDUCTOR DEVICE TESTING;
SILICON ON INSULATOR TECHNOLOGY;
THRESHOLD VOLTAGE;
VOLTAGE CONTROL;
VOLTAGE MEASUREMENT;
DOUBLE GATE TRANSISTORS;
FULLY DEPLETED TRANSISTORS;
THRESHOLD VOLTAGE CONTROL;
ULTRA THIN LAYER RESISTANCE;
MOSFET DEVICES;
|
|
EID: 0035714801
PISSN: 01631918
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
|
Times cited : (56)
|
|
References (44)
|
