Simulation Methods for ESD Protection Development

Simulation Methods for ESD Protection Development

Volumn , Issue , 2003, Pages 1-268

  Esmark, Kai ^a   Gossner, Harald ^a   Stadler, Wolfgang ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROSTATIC DEVICES;

CIRCUIT STIMULATION; COST EFFECTIVE; CRITICAL ISSUES; DEVELOPMENT CYCLE; DEVELOPMENT FLOW; DEVELOPMENT METHODOLOGY; OPTIMIZATION AND CONTROL; TECHNOLOGY DEVELOPMENT;

ELECTROSTATIC DISCHARGE;

EID: 84940878756     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1016/B978-0-08-044147-4.X5000-9     Document Type: Book

References (240)

1. Amerasekera A., Verweij J. ESD in Integrated Circuits. Quality and Reliabilty Eng. Int. 1992, 8:259.
2. Amerasekera A., Duvvury C. ESD in Silicon Integrated Circuits, Second Edition 2002, John Wiley, Chichester, England.
3. Antinone R.J. Electrical Overstress Protection for Electronic Devices 1986, Noyes Publications, New Jersey.
4. Barth J., Richner J., Verhaege K., Henry L.G. TLP-Calibration, Correlation, Standards, and New Techniques. Proc. 22nd EOS/ESD Symposium 2000, 85.
5. Barth J., Richner J. Correlation Considerations: Real HBM to TLP and HBM Testers. Proc. 23nd EOS/ESD Symposium 2001, 453.
6. BaumgÄrtner H., GÄrtner R. ESD, Elektrostatische Entladungen (in German) 1997, Oldenbourg, Munich, Germany.
7. Beebe S. Simulation of Complete CMOS I/O Circuit Response to CDM Stress. Proc. 20th EOS/ESD Symposium 1998, 259.
8. Bhar T.N., Mcmahon E.J. Electrostatic Discharge Control 1983, Hayden, NJ.
9. BÖnisch S., Pommerenke D., Kalkner W. Broadband Measurement of ESD Risetimes to Distinguish Between Different Discharge Mechanisms. Proc. 23rd EOS/ESD Symposium 2001, 373.
10. Born M., Wolf E. Principle of Optics 1980, Cambridge University Press, England.
11. Brodbeck T., Kagerer A. Influence of the Device Package on the Results of CDM Tests - Consequences for Tester Characterization and Test Procedure. Proc. 20th EOS/ESD Symposium 1998, 320.
12. Bychikhin S., Dubec V., Litzenberger M., Pogany D., Gornik E., Groos G., Esmark K., Stecher M., Stadler W., Gieser H., Wolf H. Investigation of ESD Protection Elements under High Current Stress in CDM-like Time Domain Using Backside Laser Interferometry. Proc. 24th EOS/ESD Symposium 2002, 387.
13. Corp M.B. Zzaap! Taming ESD, RFI, and EMI 1990, Academic, London.
14. Dabral S., Maloney T.J. Basic ESD and I/O Design 1998, John Wiley, New York.
15. Dangelmayer T. ESD Program Management; A Realistic Approach to Continuous Measurable Improvement in Static Control 1990, Van Nostrand Reinhold, New York.
16. Diaz C.H., Kang S.-M., Duvvury C. Modeling of Electrical Overstress in Integrated Circuits 1995, Kluwer International, Boston, Mass.
17. En 61000-4-2 Electrostatic Discharge Immunity Test 1996, Part 4, Section 2, European Standard.
18. Esd Association ESD Standard Test Method for Electrostatic Discharge Sensitivity Testing- Charged Device Model (CDM) Component Level (ESD STM5.3.1-1999) 2001, ESD Association Working Group WG 5.3.1.
19. Esd Association ESD Standard Test Method for Electrostatic Discharge Sensitivity Testing- Human Body Model (HBM) Component Level (ESD STM5.1-2001) 2001, ESD Association Working Group WG 5.1.
20. Esd Association ESD Standard Test Method for Electrostatic Discharge Sensitivity Testing- Machine Model (MM) Component Level (ESD STM5.2-1998) 1998, ESD Association Working Group WG 5.2.
21. Esd Association Socket Device Model (SDM) Tester, an application and technical report (ESD TR 08-00) 2000, ESD Association Working Group WG 5.3.2.
22. ESD Association, Standard Practice for Electrostatic Discharge Sensitivity Testing- Transmission Line Pulse (TLP) Component Level, of ESD Association Workin.
23. Frei S., Senghaas M., Jobava R., Kalkner W. The Influence of Speed of Approach and Humidity on the Intensity of ESD. Proc. EMC Symp. 1999, 105.
24. FÜrbÖck C., Pogany D., Litzenberger M., Gornik E., Seliger N., Gossner H., MÜller-Lynch T., Stecher M., Werner W. Interferometric Temperature Mapping during ESD Stress and Failure Analysis of Smart Power Technology ESD Protection Devices. Proc. 21st EOS/ESD Symp. 1999, 241.
25. FÜrbÖck C., Esmark K., Litzenberger M., Pogany D., Groos G., Zelsacher R., Stecher M., Gornik E. Thermal and Free Carrier Concentration Mapping during ESD Event in Smart Power ESD Protection Devices Using an Improved Laser Interferometric Technique. Microelectronics Reliability 2000, 40:1365.
26. Gartner R. Field-induced CDM-Ausfall in der Halbleiterfertigung (German only). Proc. 6th ESD-Forum 1999, 49.
27. Gieser H., Haunschild M. Very-Fast Transmission Line Pulsing of Integrated Structures and the Charged Device Model. Proc. 18th EOS/ESD Symposium 1996, 85.
28. Gieser H. Methods for the Characterisation of Integrated Circuits Employing Very Fast High-Current Impulses (in German). PhD thesis 1999, Technical University Munich.
29. Gieser H. Methods for the Characterisation of Integrated Circuits Employing Very Fast High-Current Impulses (in German). PhD thesis 1999, Shaker-Verlag, Aachen, Germany.
30. Gieser H. ESD in Silicon Integrated Circuits 2002, John Wiley, Chichester, England. A. Amerasekera, C. Duvvury (Eds.).
31. Greason W.D. Electrostatic Discharge in Electronics 1992, Research Studies Press, Taunton, England.
32. Iec Electrostatics, Part 3-1: Methods for Simulation of Electrostatic Effects - Human Body Model (HBM) - Component Testing 2002, 61340-3-1.
33. Iec Electrostatics, Part 3-1: Methods for Simulation of Electrostatic Effects - Machine Model (MM) - Component Testing 2002, 61340-3-2.
34. Jedec Solid State Technology Association Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM). JESD22-A114-A 1998.
35. Jedec Solid State Technology Association Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). JESD22-A114-B 2000.
36. Jedec Solid State Technology Association Field-Induced Charged Device Model Test Method for Electrostatic Discharge Withstand Thresholds for Microelectronic Components. JESD22-C101-A 2000.
37. Kessler T., Kederer F., Wulfert F.W. LiveZap - A During-the-Event Damage Site Localization Method. Proc. 7th ESD-Forum 2001, 71.
38. Lin D.L., Jon M.-C. Off-chip Protection: Shunting of ESD Current by Metal Fingers on Integrated Circuits and Printed Circuit Boards. Proc. 16th EOS/ESD Symposium 1994, 279.
39. Maier R. ESD aus Sicht eines Kfz-Herstellers (German only). Proc. 7th ESD-Forum 2001, 49.
40. Maloney T., Khurana N. Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena. Proc. 8th EOS/ESD Symposium 1985, 49.
41. Matisoff B.S. Handbook of Electrostatic Discharge Control 1986, Van Nostrand Reinhold, New York.
42. Mergens M., Wilkening W., Kiesewetter G., Mettler S., Wolf H., Hieber J., Fichtner W. ESD-level Circuit Simulation - Impact of Gate RC-Delay on HBM and CDM Robustness. Proc. 22nd EOS/ESD Symposium 2000, 446.
43. Mil Std 883.C/3015.7 Notice 8 Military Standard for Test Methods and Procedures for Microelectronics: ESD Sensitivity Classification 1989, March 22.
44. Muhoff C., Wolf H., Egger P., Gieser H., Guggenmos X. Risetime Effects of HBM and Square Pulses on the Failure Thresholds of GGNMOS Transistors. Proc. ESREF 1996, 1746.
45. Narita K., Horiguchi Y., Hayano K., Suzuki K. A Simulation Analysis of Quarter- Micron CMOS LSI Input Circuit Behaviour under CDM-ESD for Protection Device Improvement. Proc. 21st EOS/ESD Symposium 1999, 116.
46. Pogany D., Bychikhin S., Litzenberger M., Gornik E., Groos G., Stecher M. Extraction of Spatio-temporal Distribution of Power Dissipation in Semiconductor Devices Using Nanosecond Interferometric Mapping Technique. Appl. Phys. Lett. 2002, 81:2881.
47. Pogany D., Dubec V., Bychikhin S., FÜrbÖck C., Litzenberger M., Groos G., Stecher M., Gornik E. Single-Shot Thermal Energy Mapping of Semiconductor Devices With the Nanosecond Resolution Using Holographic Interferometry. IEEE Electr. Dev. Lett. 2002, 23:606.
48. Pogany D., Bychikhin S., FÜrbÖck C., Litzenberger M., Gornik E., Groos G., Esmark K., Stecher M. Quantitative Internal Thermal Energy Mapping of Semiconductor Devices under Short Current Stress Using Backside Laser Interferometry. IEEE Trans. Electr. Dev. 2002, 49:2070.
49. Rainer J.C., Keller T., JÄggi H., Mira S. Impact of ESD-induced Soft Drain Junction Damage on CMOS Product Lifetime. Microelectr. Reliability 2000, 40:1649.
50. Renninger R.G., Jon M., Lin D.L., Diep T., Welsher T.L. A Field-Induced Charged Device Model Simulator. Proc. 11th EOS/ESD Symposium 1989, 59.
51. Renninger R.G. Mechanisms of Charged Device Model Electrostatic Discharges. Proc. 13th EOS/ESD Symposium 1991, 127.
52. Microelectronic Failure Analysis, Proceeding of the ASM International 1999, R. Roas, C. Boit, S. Staab (Eds.).
53. Roozendaal Van L.J., Amerasekera A., Bos P., Baelde W., Bontekoe F., Kersten P., Korma E., Rommers P., Krys P., Weber U., Ashby P. Standard ESD Testing. Proc. 12th EOS/ESD Symposium 1990, 119.
54. Russ C., Gieser H., Verhaege K. ESD Protection Elements During HBM-ESD-stress tests - Further Numerical and Experimental Results. Proc. 16th EOS/ESD Symposium 1994, 96.
55. Russ C., Verhaege K., Bock K., Roussel P.J., Groeseneken G., Maes H.E. A Compact Model for the Grounded-Gate nMOS Behaviour under CDM ESD Stress. Proc. 18th EOS/ESD Symposium 1996, 302.
56. Russ C., Bock K.-H., Rasras M., De Wolf I., Groeseneken G., Maes H.E. Non-Uniform Triggering of gg-nMOSt Investigated by Combined Emission Microscopy and Transmission Line Pulsing. Proc. 20th EOS/ESD Symposium 1998, 177.
57. Shaw R.N., Enoch R.D. An Experimental Investigation of ESD-Induced Damage to Integrated Circuits on Printed Circuit Boards. Proc. 7th EOS/ESD Symposium 1985, 132.
58. Stadler W., Guggenmos X., Egger P., Gieser H., Muhoff C. Does the ESD Failure Current Obtained by Transmission Line Pulsing Always Correlate to Human Body Model Tests?. Proc. 19th EOS/ESD Symposium 1997, 366.
59. Verhaege K., Roussel P.J., Groeseneken G., Maes H.E., Gieser H., Russ C., Egger P., Guggenmos X., Kuper F.G. Analysis of HBM ESD testers and Specifications Using 4th Order Lumped Element Model. Proc. 15th EOS/ESD Symposium 1993, 129.
60. Wang A.Z.H. On-Chip ESD Protection for Integrated Circuits 2002, Kluwer Academic Publishers, Boston.
61. Wilkening W., Stadler W., Willemen J., Esmark K., Wolf H., Gieser H. Investigations on Charged Device Model for On-Chip ESD Protection in the ASDESE Project. Proc. 7th ESD-Forum 2001, 87.
62. Yan K.P., GÄrtner R., Lim S. A Study of Wafer Level ESD Testing. Proc. 23rd EOS/ESD Symposium 2001.
63. Yokoi K., Watanabe T. An Effective ESD Protection System in the Back End (BE) Semiconductor Manufacturing Facility. Proc. 22th EOS/ESD Symposium 2000, 1.
64. Amerasekera A., Chatterjee A. An Investigation of BiCMOS ESD Protection Circuit Elements and Applications in Submicron Technologies. Proc. 14th EOS/ESD Symposium 1992, 265.
65. Amerasekera A., Chang M.-C., Seitchik J., Chatterjee A., Mayaram K., Chern J.-H. Self-heating Effects in Basic Semiconductor Structures. IEEE Electr. Dev. 1993, 1836.
66. Amerasekera A., Duvvury C. ESD in Silicon Integrated Circuits, Second Edition 2002, John Wiley, Chichester, England.
67. Avery L. Using SCRs as Transient Protection Structures in Integrated Circuits. Proc. 5th EOS/ESD Symposium 1983, 177.
68. Banerjee K., Amerasekera A., Kittl J., Hu C. High Current Effects in Suicide Films for Sub-0.25 m VLSI Technologies. Proc. IRPS 1998, 284.
69. Carbajal B., Cline R., Andersen B. A Successful HBM ESD Protection Circuit for Micron and Sub-Micron Level CMOS. Proc. 14th EOS/ESD Symposium 1992, 234.
70. Chatterjee A., Seitchik J.A., Chern J.-H., Wang P., Wei C.-C. Direct Evidence Supporting the Premises of a Twodimensional Diode Model for the Parasitic Thyristor in CMOS Circuits Built on Thin Epi. IEEE Trans. Electr. Dev. 1988, 509.
71. Chatterjee A., Polgreen T. A Low-Voltage Triggering SCR for On-chip Protection at Output and Input Pads. Electr. Dev. Lett. 1991, 21.
72. Chatterjee A, Polgreen T., Amerasekera A. Design and Simulation of a 4 kV ESD Protection Circuit for a 0.8 urn BiCMOS process. Tech. Dig. IEDM 1991, 913.
73. Corsi M., Nimmo R., Fattori F. ESD Protection of BiCMOS Integrated Circuits which Need to Operate in the Harsh Environments of Automotive or Industrial. Proc. 15th EOS/ESD Symposium 1993, 209.
74. Dabral S., Maloney T.J. Basic ESD and I/O Design 1998, John Wiley, New York.
75. Duvvury C., Rountree R.N., Adams G. Internal Chip ESD Phenomena beyond the Protection Circuit. IEEE Trans. Electr. Dev. 1988, 2133.
76. Duvvury C., Amerasekera A. Advanced CMOS Protection Device Triggermechanisms During CDM. Proc. 17th EOS/ESD Symposium 1995, 162.
77. Esmark K., Stadler W., Gossner H., Wendel M., Guggenmos X., Fichtner W. Advanced 2D/3D ESD Device Simulation - a Powerful Tool Already Used in a Pre-Si Phase. Proc. 22nd EOS/ESD Symposium 2000, 420.
78. Esmark K., Stadler W., Gossner H., Wendel M., Guggenmos X., Fichtner W. Advanced 2D/3D ESD Device Simulation - a Powerful Tool Already Used in a Pre-Si Phase. Microelectronic Reliability 2001, 41:1761.
79. Gossner H., MÜller-Lynch T., Esmark K., Stecher M. Wide Range Control of the Sustaining Voltage of ESD Protection Elements Realized in a Smart Power Technology. Proc. 21st EOS/ESD Symposium 1999, 19.
80. Herlet A., Raithel K. Forward Characteristics of Thyristors in the Fired State. J. Solid State Electr. 1966, 1089.
81. Hower P.L., Gopala K.R.V. Avalanche Injection and Second Breakdown in Transistors. IEEE Trans. Electr. Devices 1970, 320.
82. Jaffe M., Cottrell P.E. Electrostatic Discharge Protection in a 4-Mbit DRAM. Proc. 12th EOS/ESD Symposium 1990, 218.
83. Johnson C.C., Qawami S., Maloney T.J. Two Unsusual Failure Mechnisms on a Mature CMOS Process. Proc. 15th EOS/ESD Symposium 1993, 225.
84. Ker M.D., Wu C.Y., Lee C. A Novel CMOS ESD/EOS Protection Circuit with Full-SCR Structures. Proc. 14th EOS/ESD Symposium 1992, 258.
85. Ker M.D., Wu C.Y., Cheng T., Chang H.H. Capacitor-Coupled ESD Protection Circuit for Deep-Submicron Low-Voltage CMOS ASIC. IEEE Trans. VLSI Systems 1996, 307.
86. Khurana B.S., Sugano T., Yanai H. Thermal Breakdown in Silicon p-n Junction Devices. IEEE Trans. Electr. Devices 1966, 763.
87. Krieger G. The Dynamics of Electrostatic Discharge Prior to Bipolar Action Related Snapback. Proc. 11th EOS/ESD Symposium 1989, 136.
88. Maloney T.J., Dabral S. Novel Clamp Circuits for IC Power Supply Protection. Proc. 18th EOS/ESD Symposium 1995, 1.
89. Russ C.C., Mergens M.P.J., Armer J., Jozwiak P.C., Kolluri G., Avery L.R., Verhaege K.G. GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Processes. Proc. 23rd EOS/ESD Symposium 2001, 22.
90. Sanchez H., Siegel J., Nicoletta C., Alvarez J., Nissen J. A Versatile 3.3 V/2.5 V/1.8 V CMOS I/O Driver Built in a 0.2 μm 3.5 nm Tox 1.8 V Technology. Tech. Dig. ISSCC 1999, 276.
91. Seitchik J., Chatterjee A., Yang P. An Analytical Model of Holding Volatge for Latchup in Epitaxial CMOS. IEEE Electr. Dev. Lett. 1987, 157.
92. Streibl M., Esmark K., Sieck A., Stadler W., Wendel M., Szatkowski J., Gossner H. Harnessing the Base-Pushout Effect for ESD Protection in Bipolar and BiCMOS Technologies. Proc. 24th EOS/ESD Symposium 2002, 73.
93. Voldman S.H. ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Enviroment in 0.5-and 0.25m Channel Length CMOS Technologies. Proc. EOS/ESD Symposium 1994, 125.
94. Voldman S.H., Gerosa G., Gross V.P., Dickson N., Furkay S., Slinkman J. Analysis of Snubber-Clamped Diode-String Mixed Voltage Interface ESD Protection Network for Advanced Microprocessors. Proc. 17th EOS/ESD Symposium 1995, 43.
95. Yang P., Chern J.-H. Design for Reliabilty: The Major Challenge for VLSI. Proc. IEEE 1993, 730.
96. Amerasekera A., Duvvury C. ESD in Silicon Integrated Circuits, Second Edition 2002, John Wiley, Chichester, England.
97. Gauthier R., Stadler W., Esmark K., Riess P., Salman A., Muhammad M., Putnam C. Evaluation of Diode-Based and nMOS/Lnpn-Based ESD Protection Strategies in a Triple Gate Oxide Thickness 0.13 μm CMOS Logic Technology. Proc. 23rd EOS/ESD Symposium 2001, 205.
98. Maloney T. Novel Clamp Circuits for IC Power Supply Protection. Proc. 17th EOS/ESD Symposium 1995, 1.
99. Massobrio G., Antognetti P. Semiconductor Device Modeling with SPICE 1993, McGraw-Hill, New York.
100. Never J., Voldman S. Failure Analysis of Shallow Trench Isolation ESD Structures. Proc. 17th EOS/ESD Symposium 1995, 273.
101. Sematech Esd Technology Working Group Test Structures for Benchmarking the Electrostatic Discharge (ESD) Robustness of CMOS Technologies. SEMATECH Technology Transfer # 98013452A-TR 1998.
102. Biersack J.P., Haggemark L.G. A Monte Carlo Computer Program for the Transport of Energetic Ions in Amorphous Targets. Nuclear Instruments and Methods 1980, 174:257.
103. Carey G.F., Richardson W.B., Reed C.S., Mulvaney B.J. Circuit, Device and Process Simulation- Mathematical and Numerical Aspects 1996, John Wiley, New York.
104. Hobler G., Selberherr S. Two-Dimensional Modeling of Ion Implantation Induced Point Defects. IEEE Trans, on CAD 1988, 7:174.
105. Osburne C.M., Tsai J.Y., Sun J. Active Elements of ULSI Contacts. J. Electronic Mat. 1996, 25:1725.
106. Rafferty C.S., Vuong H.-H., Esraghi S.A., Giles M.D., Pinto M.R., Hillenius S.J. Explanation of Reverse Short Channel Effect by Point Gradients. Proc. IEDM 1993, 311.
107. Selberherr S. Analysis and Simulation of Semiconductor Devices 1984, Springer, Wien.
108. Sze S.M. Semiconductor Devices- Physics and Technology 1985, John Wiley, New York.
109. Ukraintsev V.A., Walsh S.T., Ashburn S.P., Machala C.F., Edwards H., Gray J.T., Joshi S., Woodall D., Chang M.-C. Two Dimensional Dopant Characterization Using SIMS, SCS and TSUPREM4. Proc. IEDM 1999, 349.
110. Abderhalden J. Untersuchung zur Optimierung von Schutzstrukturen gegen Elektrostatische Entladungen in Integrierten CM OS-Schaltungen (in German). PhD thesis 1990, Swiss Federal Institute for Technology.
111. Amerasekera A., Seitchik J. Electrothermal Behavior of Deep Submicron nMOS Transistors under High Current Snapback (ESD/EOS) Conditions. Proc. IEDM 1994, 446.
112. Amerasekera A., Duvvury C. ESD in Silicon Integrated Circuits, Second Edition 2002, John Wiley, Chichester, England.
113. Baliga B.J. Modern Power Devices 1987, John Wiley, New York.
114. Bank R.E., Rose D.J., Fichtner W. Numerical Methods for Semiconductor Device Simulation. IEEE Transact. Electr. Dev. 1983, ED-30:1031.
115. Bargstaedt S., Oettinger K. Advanced 2D Latch-up Device Simulation- a Powerful Tool During Development in the Pre-silicon Phase. Proc. IRPS 2001, 235.
116. Benvenuti A., Ghione G., Pinot M.-R., Coughra W.-M, Schryer N.-L. Coupled Thermal - Fully Hydrodynamic Simulation of InP Based HBTs. IEDM 1992, 737.
117. Bock K.-H., Keppens G., De Heyn V., Groesenecken G., Chiang L.Y., Naem A. Influence of Gate Length on ESD Performance for Deep Submicron CMOS Technologies. Proc. 21st EOS/ESD Symposium 1999, 95.
118. Boselli G., Meeuwsen S., Mouthaan T., Kuper F. Investigations on Double-diffused MOS Transistors under ESD Zap Conditions. Microelectronics Reliability 2001, 41:395.
119. Bufler F.M., Asahi Y., Yoshimura H., Zechner C., Schenk A., Fichtner W. Monte Carlo Simulation and Measurement of Nanoscale n-MOSFETs. IEEE Trans. Elec. Dev. 2003.
120. Chen D., Yu Z., Wu K.-C., Grossens R., Dutton R.W. Dual Energy Transport Model with Coupled Lattice and Carrier Temperature. Proc. SISDEP 1993, 157.
121. Chynoweth A. Ionization Rates for Electrons and Holes in Silicon. Phys. Rev. 1958, 109:1537.
122. Chynoweth A. Uniform Silicon p-n Junctions II. Ionization Rates of Electrons. J. Appl. Phys. 1960, 31:1161.
123. Duvvury C., Amerasekera A., Joyner K., Ramaswamy S., Young S. ESD Design for Deep Submicron SOI Technologies. Proc. VLSI Symposium Techn. 1996, 194.
124. Dessis-Ise Reference Manual ISE Integrated Systems Engineering AG 1998, Zurich, Switzerland.
125. ESD Standard Test Method for Electrostatic Discharge Sensitivity Testing- Human Body Model (HBM) Component Level (ESD STM5.1-2001), of ESD Association Wo 2001.
126. Wilkening W. ESPRIT Project ESDEM. Proc. Public Workshop of the ESDEM, Institute for Integrated Systems 1999, ETH Zurich.
127. Esmark K., FÜrbÖck C., Gossner H., Gross G., Litzenberger M., Pogany D., Zelsacher R., Stecher M., Gornik E. Simulation and Experimental Study of Temperature Distribution During ESD Stress in Smart-Power-Technology ESD Protection Structures. Proc. IRPS 2000, 304.
128. Esmark K. Device Simulation of ESD Protection Elements. PhD thesis 2001, Swiss Federal Institute for Technology.
129. Esmark K. Device Simulation of ESD Protection Elements. PhD thesis 2001, published, Hartung-Gorre-Verlag, Konstanz, Germany.
130. Esmark K., Stadler W., Gossner H., Wendel M., Streibl M., Fichtner W. ESD Schutzkonzeptentwicklung mit 2D-und 3D-Bausimulation - kann man auf Silizium verzichten (available in German only). Proc. 7th ESD-Forum 2001, 95.
131. Fong Y., Hu C. The Effects of High Electric Field Transients on Thin Gate Oxide MOSFETs. Proc. 9th EOS/ESD Symposium 1987, 252.
132. Fong Y., Hu C. High Current Snapback Characteristic for MOSFETs. IEEE Trans. Electr. Dev. 1990, 37:2101.
133. Ghandi S.K. Semiconductor Power Devices 1978, John Wiley, New York.
134. Groeseneken G. Hot Carrier Degradation and ESD in Submicron CMOS Technologies: How do they Interact?. 22nd EOS/ESD Symposium 2000, 276.
135. Grutchfield H.B., Moutoux T.J. Current mode second breakdown in epitaxial planar transistors. IEEE Trans. Electr. Dev. 1966, 11:743.
136. HÄcker R., Hangleiter A. Intrinsic Upper Limits of Carrier Lifetime in Silicon. J. Appl. Phys. 1994, 75:7570.
137. HÄnsch W. The Drift Diffusion Equation and Its Applications in MOSFET Modeling 1991, Springer, Wien.
138. Hirsch I., Berman E., Haik N. Thermal Resistance Evaluation in 3-D thermal simulation of MOSFET transistors. Solid State Electronics 1993, 36:106.
139. Ieong M., Tang T. Influence of Hydrodynamic Models on the Prediction of Submicrom-eter Device Characteristics. IEEE Trans. Elec. Dev. 1997, 44:2242.
140. Jacoboni C., Lugli P. The Monte Carlo Method for Semiconductor Device Simulation 1989, Springer, Wien.
141. Lackner T. Avalanche Multiplication in Semiconductors: A modification of Chynoweth's Law. Solid State Electr. 1991, 34:33.
142. Maes W., De Meyer K., Van Overstraten R. Impact Ionization in Silicon: A Review and Update. Solid State Electr. 1990, 33:705.
143. Miller J., Khazhinsky M., Weldon J. Engineering the Cascoded NMOS Buffer for Maximum Vu. Proc. EOS/ESD Symposium 2000, 308.
144. Muhoff C., Wolf H., Egger P., Gieser H., Guggenmos X. Risetime Effects of HBM and Square Pulses on the Failure Thresholds of GGNMOS Transistors. Proc. ESREF 1996, 1746.
145. Ning T.H. Silicon Technology Directing in the new Millenium. Proc. IRPS 2000, 1.
146. Noetermans G. On the Use of N-Well Resistors for Uniform Triggering of ESD Protection Elements. Proc. 19th EOS/ESD Symposium 1997, 221.
147. Okuto Y., Crowell C.R. Threshold Energy Effects on Avalanche Breakdown Voltage in Semiconductor Junctions. Solid State Electr. 1975, 18:161.
148. Overstraten Van R., de Man H. Measurements of the Ionization Rates in Diffused Silicon p -n Junctions. Solid State Electr. 1970, 13:583.
149. Parasitics (Funding Project of the German Federal Ministry Of Education Science) Simulation Statischer und Dynamischer Durchbruch (in German only). Final Report 2000.
150. Perko L. Differential Equations and Dynamical Systems 1991, Springer, New York.
151. Pierantoni A., Liuzzo A., Ciampolini P., Baccarani G. Three-Dimensional Implementation of a Modified Transport Model. Proc. SISDEP 1993, 125.
152. Pogany D., Esmark K., Litzenberger M., FÜrbÖck C., Goner H., Gornik E. Bulk and Surface Degradation Mode in 0.35 μm technology gg-nMOS ESD protection devices. Proc. ESREF 2000, 1467.
153. Russ C. ESD Protection Devices for CMOS Technologies: Processing Impact, Modeling, and Testing Issues. PhD thesis 1999, Technical University Munich.
154. Russ C. ESD Protection Devices for CMOS Technologies: Processing Impact, Modeling, and Testing Issues. PhD thesis 1999, published, Shaker-Verlag, Aachen, Germany.
155. Russ C., Mergens M.P.J., Verhaege K.G., Arner J., Jozwika P.C., Kolluri G., Avery L.R. GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep sub-micron CMOS Processes. Proc. 23rd EOS/ESD Symposium 2001, 22.
156. Salman A., Gauthier R., Furkay S., Muhammad M., Putnam C., Ioannou D., Nguyen P., Stadler W., Esmark K. Characterization and Investigation of the Interaction Between Hot Electron and Electrostatic Discharge Stresses Using NMOS Devices in 0.13 μm Technology. Proc. IRPS 2001, 219.
157. Schenk A. Advanced Physical Models for Device Simulation 1998, Springer, Wien.
158. Shockley W. Problems Related to p-n Junction in Silicon. Solid State Electr. 1961, 2:35.
159. Seeger K. Semiconductor Physics 1991, Springer, Berlin.
160. Selberherr S. Analysis and Simulation of Semiconductor Devices 1984, Springer, Wien.
161. Slotboom J.W., Van Dort M.J., Hurkx G.A.M., Klaase D.B.M., Kloosterman W.J., Van Rijs F., Streutker G., Velghe D. Physical Modeling and Simulation of Advanced Si-Devices - An Industrial Approach. Proc. ESSDERC 1993, 327.
162. Stadler W., Guggenmos X., Egger P., Gieser H., Muhoff C. Does the ESD Failure Current Obtained by Transmission Line Pulsing Always Correlate to Human Body Model Tests?. Proc. 19th EOS/ESD Symposium 1997, 366.
163. Stadler W., Esmark K., Reynders K., Zubeidat M., Graf M., Wilkening W., Wille-Men J., Qu N., Mettler S., Etherton M., Wolf H., Gieser H., Soppa W., De Heyn V., Natarajan M., Groeseneken G., Morena E., Stella R., Andreini A., Litzenberger M., Pogany D., Gornik E., Foss C., Nuernbergk D., Konrad A., Frank M. Test Circuits for Fast and Reliable Assessment of CDM Robustness of I/O stages. 25th EOS/ESD symposium 2003, accepted for publication.
164. Streibl M., Esmark K., Sieck A., Stadler W., Wendel M., Szatkowski J., Gossner H. Harnessing the Base-Pushout Effect for ESD Protection in Bipolar and BiCMOS Technologies. Proc. 24th EOS/ESD Symposium 2002, 73.
165. Stricker A. Technology Computer Aided Design of ESD Protection Devices. PhD thesis 2000, Swiss Federal Institute for Technology.
166. Stricker A. Technology Computer Aided Design of ESD Protection Devices. PhD thesis 2000, published, Hartung-Gorre-Verlag, Konstanz, Germany.
167. Sze S.M. Physics of Semiconductor Devices 1981, John Wiley and Sons, New York. 2nd Edition.
168. Valdinoci M., Ventura D., Vecchi M.C., Ruda M., Baccarani G., Illien F., Stricker A., Zullino L. Impact Ionization at Large Operating Temperatures. Proc. SISDEP 1999, 27.
169. Verhaege K., Roussel P.J., Groeseneken G., Maes H.E., Gieser H., Russ C., Egger P., Guggenmos X., Kuper F.G. Analysis of HBM ESD Testers and Specifications Using 4th Order Lumped Element Model. Proc. 15th EOS/ESD Symposium 1993, 129.
170. Voldman S.H., Botula A., Hui D.T., Juliano P.A. Silicon Germanium Heterojunction Bipolar Transistor ESD Power Clamps and the Johnson Limit. Proc. 23rd EOS/ESD Symposium 2001, 326.
171. Wachutka G.K. Rigorous Thermodynamic Treatment of Heat Generation and Conduction in Semiconductir Device Modeling. IEEE Trans. CAD Integr. Circuits and Systems 1990, 1141.
172. Wachutka G.K. Unified Framework for Thermal, Eelectrical, Magnetic and Optical Semiconductor device Modeling. COMPEL 1991, Vol 10(No 4):311.
173. Wilkening W., Stadler W., Willemen J., Esmark K., Wolf H., Gieser H. Investigations on Charged Device Model for On-Chip ESD Protection in the ASDESE Project. Proc. 7th ESD-Forum 2001, 87.
174. Wu J., Juliano P., Rosenbaum E. Breakdown and Latent Damage of Ultra-Thin Gate Oxides under ESD Stress Conditions. Proc. 22th EOS/ESD Symposium 2000, 287.
175. Wunsch D.C., Bell R.R. Determination of Threshold Failure Levels of Semiconductor Diodes and Transistors due to Pulse Voltage. IEEE Trans. Nucl. Sci. 1968, 15:244.
176. Yu B., Wang H., Joshi A., Xiang Q., Ibok E., Lin M.-R. 15 nm Gate Length Planar CMOS Transistor. IEDM 2001 2001, Washington DC.
177. Amerasekera A., Chang M.C., Seitchik J., Chatterjee A., Majaram K., Chen J.C. Self-heating Effects in Basic Semiconductor Structures. IEEE Electronic Devices 1993, 1836.
178. Amerasekera A., Duvvury C. ESD in Silicon Integrated Circuits 2002, John Wiley, Chichester, England. Second Edition.
179. Amerasekera A., Ramaswamy S., Chang M.C., Duvvury C. Modeling MOS Snapback and Parasitic Bipolar Action for Circuit-Level ESD and High Current Simulations. Proc. IRPS 1996, 318.
180. Beebe S. Simulation of Complete CMOS I/O Circuit Response to CDM Stress. Proc. 20th EOS/ESD Symposium 1998, 259.
181. Blicher A. Field-Effect and Bipolar Power Transistor Physic 1981, Academic Press, New York.
182. Boselli G., Ramaswamy S., Amerasekera A., Mouthaan T., Kuper F. Modelling Substrate Diodes under Ultra-High ESD Injection Conditions. Proc. 23th EOS/ESD Symposium 2001, 71.
183. Carbajal B., Cline R., Andersen B. A Successful HBM ESD Protection Circuit for Micron and Sub-Micron Level CMOS. Proc. 14th EOS/ESD Symposium 1992, 234.
184. Chynoweth A. Uniform Silicon p-n Junctions II. Ionization Rates of Electrons. J. Appl. Phys. 1960, 31:1161.
185. Diaz C., Kang S., Duvvury C. Circuit-level Electrothermal Simulation of Electrical Overstress Failures in Adanced MOS I/O Protection Devices. IEEE Trans. CAD 1994, 13:482.
186. Dutton R.W. Bipolar Transistor Modeling of Avalanche Generation for Computer Circuit Simulation. IEEE Trans. Electr. Devices 1975, 22:334.
187. Ebers J.J., Moll J.N. Large-Signal Behavior of Junction Transistors. Proc. IRE 1954, 42:1761.
188. Gao X.F., Liou J.J., Ortiz-Conde A., Bernier J., Croft G. A Physics-based Model for the Substrate Resistance of MOSFET's. Solid State Electr. 2002, 46:853.
189. Gao X.F., Liou J.J., Bernier J., Croft G., Ortiz-Conde A. Implementation of a Comprehensive and Robust MOSFET Model in Cadence SPICE for ESD Applications. IEEE Trans. CAD 2002, 21:1497.
190. Gieser H., Haunschild M. Very-Fast Transmission Line Pulsing of Integrated Structures and the Charged Device Model. Proc. EOS/ESD Symposium 1996, 85.
191. Gummel H.K., Poon H.C. An Integral Charge Control Model of Bipolar Transistors. Bell Syst. Tech. Journal 1970, 49:827.
192. Hsu F.-C., Ko P.-K., Tarn S., Hu C., MÜller R.S. An Analytical Breakdown Model for Short-Channel MOSFET's. Proc. EOS/ESD Symposium 1996, 85.
193. Ise Integrated Systems Engineering Ag Switzerland ISE TCAD Manuals 1998, Release 5.0, Part 14, DESSIS.
194. Joshi S., Rosenbaum E. Compact Modeling of Vertical ESD Protection npn Transistors for RF Circuits. Proc. 24th EOS/ESD Symposium 2002, 289.
195. Juliano P., Rosenbaum E. A Novel SCR Macromodel for ESD Circuit Simulation. Int. Electron Devices Meeting Tech. Dig. 2001, 319.
196. Kittel C. Introduction to Solid State Physics 1983, John Wiley and Sons, New York. 6th Edition.
197. Kurimoto K., Yamashita K., Miyanaga I., Hori A., Odanaka S. An Electrothermal Circuit Simulation Using an Equivalent Thermal Network for Electrostatic Discharge (ESD). Proc. VLSI Techn. Symposium 1994, 127.
198. Li T., Suh D., Ramaswamy S., Bendix P., Rosenbaum E., Kapoor A., Kang S.M. Study of a CMOS I/O Protection Circuit Using Circuit-Level Simulation. Proc. IRPS 1997, 333.
199. Li T., Tsai C.-H., Rosenbaum E., Kang S.-M. Substrate Resistance Modeling and Circuit-level Simulation of Parasitic Device Coupling Effects for CMOS I/O Circuits under ESD Stress. Proc. 20th EOS/ESD Symp. 1998, 281.
200. Lim S.L., Zhang X., Beebe S., Dutton R.W. A Computationally Stable Quasi-Empirical Compact Model for the Simulation of MOS breakdown in ESD protection Circuit Design. Proc. SISPAD 1997, 161.
201. Luchies J.R.M., De Koert C.G.C.M., Verweij J.F. Fast Turn-on of an NMOS ESD Protection Transistor Measurements and Simulations. Proc. 16st EOS/ESD Symposium 1994, 266.
202. Ma C.L., Lauritzen P.O., Sigg J. Modeling of Power Diodes with the Lumped-Charge Modeling Technique. IEEE Transactions on PowerElectronics 1997, 12:398.
203. Massobrio G., Antognetti P. Semiconductor Device Modeling with SPICE 1993, McGraw-Hill, New York.
204. Mergens M., Wilkening W., Mettler S., Wolf H., Stricker A., Fichtner W. Analysis and Compact Modeling of Lateral DMOS Power Devices Under ESD Stress Conditions. Proc. 21st EOS/ESD Symposium 1999, 1.
205. Mergens M., Wilkening W., Mettler S., Wolf H., Fichtner W. Modular Approach of a High Current MOS Compact Model for Circuit-level ESD Simulation Including Transient Gate-coupling Behavior. Proc. IRPS 1999, 167.
206. Mergens M., Wilkening W., Kiesewetter G., Mettler S., Wolf H., Hieber J., Fichtner W. ESD-level Circuit Simulation - Impact of Gate RC-Delay on HBM and CDM robustness. Proc. 22nd EOS/ESD Symposium 2000, 446.
207. Mergens M. On-Chip ESD Protection in Integrated Circuits: Device Physics, Modeling, Circuit Simulation. PhD thesis 2001, ETH Zurich.
208. Mergens M. On-Chip ESD Protection in Integrated Circuits: Device Physics, Modeling, Circuit Simulation. PhD thesis 2001, published, Hartung-Gorre-Verlag, Konstanz.
209. Miller S. Ionization Rates for Holes and Electrons in Silicon. Phys. Rev. Lett. 1957, 105:1246.
210. Muller R.S., Kamins T.I. Device Electronics for Integrated Circuits 1986, John Wiley and Sons, New York. 2nd Edition.
211. Puvvada V., Duvvury C. A Simulation Study of HBM Failure in an Internal Clock Buffer and the Design Issue for Efficient Power Pin Protection Strategy. Proc. 20th EOS/ESD Symposium 1998, 104.
212. Puvvada V., Srinivasan V., Gupta V. A Scalable Analytical Model for the ESD N-Well resistor. Proc. 22th EOS/ESD Symposium 2000, 437.
213. Raha P., Ramaswamy S., Rosenbaum E. Heat Flow Analysis for EOS/ESD Protection Device Design in SOI Technology. IEEE Trans. Electr. Dev. 1997, 464.
214. Ramaswamy S., Li E., Rosenbaum E., Kang S.-M. Circuit-level Simulation of CDM-ESD and EOS in Submicron MOS Devices. Proc. 18th EOS/ESD Symposium 1996, 316.
215. Russ C., Gieser H., Egger P., Irl S. Compact Electro-Thermal Simulation of ESD-Protection Elements. Proc. ESREF 1993, 395.
216. Russ C., Verhaege K., Bock K., Roussel P.J., Groesenecken G., Maes H.E. A Compact Model for the Grounded-Gate nMOS Behavour under CDM ESD Stress. Proc. 18th EOS/ESD Symposium 1996, 302.
217. Russ C. ESD Protection Devices for CMOS Technologies: Processing Impact, Modeling, and Testing Issues. PhD thesis 1999, Technical University Munich.
218. Russ C. ESD Protection Devices for CMOS Technologies: Processing Impact, Modeling, and Testing Issues. PhD thesis 1999, published, Shaker-Verlag, Aachen, Germany.
219. Shockley W. Electrons and Holes in Semiconductors 1950, Van Nostrand, Princeton (N.J.).
220. Stricker A.D., Mettler S., Wolf H., Mergens M., Wilkening W., Gieser H., Fichtner W. Characterization and Optimization of a Bipolar ESD-Device by Measurements and Simulations. Proc. 20nd EOS/ESD Symposium 1998, 290.
221. Sze S.M. Physics of Semiconductor Devices 1981, John Wiley and Sons, New York. 2nd Edition.
222. Sze S.M. Modern Semiconductor Device Physics 1997, John Wiley and Sons, New York.
223. Verhaege K., Russ C., Robinson-Hahn D., Farris M., Scanlon J., Lin D., Veltri J., Groe-Senecken G. Recommendations to Further Improvements of HBM Component Level Test Specifications. Proc. 18th EOS/ESD Symposium 1996, 40.
224. Wang Y., Juliano P., Joshi S., Rosenbaum E. Electrothermal Modeling of ESD Diodes in Bulk-Si and SOI Technologies. Proc. 22nd EOS/ESD Symposium 2000, 430.
225. Wolf H., Gieser H., Wilkening W. Pulsed Thermal Characterisation of a Reverse Biased PN-Junction for ESD HBM Simulation. Microel. Rel. 1996, 36:1711.
226. Wolf H., Gieser H., Stadler W. Bipolar Model Extension for MOS Transistors Considering Gate Coupling Effects in the HBM ESD Domain. Proc. 20nd EOS/ESD Symposium 1998, 271.
227. Wolf H., Gieser H., Wilkening W. Analyzing the Switching Behavior of ESD-Protection Transistors by Very-Fast Transmission Line Pulsing. J. Electrostatics 2000, 49:111.
228. Wolf H., Gieser H., Stadler W., Esmark K. ESD Circuit Simulation for the Prevention of ESD Failures - Application to Products in a 0.18 m Technology. Proc. IRPS 2001, 430.
229. Baird M., Ida R. Verify ESD: A Tool for Efficient Circuit Level ESD Simulation of Mixed-Signal ICs. Proc. EOS/ESD Symposium 2000, 465.
230. Bass S., Nickel D., Sullivan D., Voldman S. Method of Automated ESD Protection Level Verification 2000, US Patent 6086627.
231. Duvvury C., Roundtree R., Adams O. Internal Chip ESD Phenomena Beyond the Protection Circuit. IEEE Trans. Electr. Dev. 1988, 2133.
232. Johnson C., Qawami S., Maloney T. Two Unusual HBM ESD Failure Mechanisms on a Mature CMOS Process. Proc. EOS/ESD Symposium 1993, 225.
233. Jedec Solid State Technology Association Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). JESD22-A114-B 2000.
234. Kang S-M.S., Duvvury C., Diaz C.H., Ramaswamy S. Methods, Apparatus and Computer Program Products for Synthesizing Integrated Circuits with Electrostatic Discharge Capability and Connecting Ground Rules Faul 1998, US Patent 5796638.
235. Lee J., Huh Y., Chen J.W., Bendix P., Kang S.-M. Chip-Level Simulation for CDM Failures in Multi-Power ICs. Proc. EOS/ESD Symposium 2000, 456.
236. Ngan P., Gramacy R., Wong C.-K., Oliver D., Smedes T. Automated Layout Based Verification of Electrostatic Discharge Paths. Proc. EOS/ESD Symposium 2001, 96.
237. Puvvada V., Duvvury C. A Simulation Study of HBM Failure in an Internal Cluck Buffer and the Design Issue for Efficient Power Pin Protection Strategy. Proc. 20th EOS/ESD Symposium 1998, 104.
238. Sinha S., Swaminathan H., Kadamati G., Duvvury C. An Automated Tool for Detecting ESD Design Errors. Proc. EOS/ESD Symposium 1998, 208.
239. Streibl M., ZÄngl F., Esmark K., Schwencker R., Stadler W., Gossner H., DrÜen S., Schmitt-Landsiedel D. High Abstraction Level Permutational ESD Concept Analysis. EOS/ESD Symposium 2003, accepted for publication.
240. Venugopal P., Sinha S., Ramaswamy S., Duvvury C., Prasad G., Raghu Kadamati G. Integrated Circuit Design Error Detector for Electrostatic Discharge and Latch-up Applications 2002, US Patent 6493850B2.