Investigation of ESD protection elements under high current stress in CDM-like time domain using backside laser interferometry

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn 2002-January, Issue , 2002, Pages 390-398

  Bychikhin, S ^a   Dubec, V ^a   Litzenberger, M ^a   Pogany, D ^a   Gornik, E ^a   Groos, G ^b   Esmark, K ^b   Stecher, M ^b   Stadler, W ^b   Gieser, H ^c   Wolf, H ^c  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^b INFINEON TECHNOLOGIES AG   (Germany)

^c Fraunhofer Institute Reliability and Microintegration   (Germany)

Author keywords

CMOS technology; Diodes; Electrostatic discharge; Electrostatic interference; Integrated circuit modeling; Interferometry; Internal stresses; Protection; Thermal stresses; Thyristors

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIODES; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; ELECTROSTATICS; INTERFEROMETRY; LASER INTERFEROMETRY; RESIDUAL STRESSES; THERMAL STRESS; THYRISTORS;

CMOS TECHNOLOGY; ELECTROSTATIC INTERFERENCE; ESD PROTECTION DEVICES; HIGH CURRENT STRESS; INTEGRATED CIRCUIT MODELING; OPTICAL TRANSIENT; PROTECTION; SWITCHING DYNAMICS;

TIME DOMAIN ANALYSIS;

EID: 84948743951     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (28)

1. A. Amerasekera, and J. Verwey, "ESD in integrated circuits", Qual. Rel. Eng. Int., vol. 8, 1992, pp. 259-272.
2. K. Verhaege, C. Russ, J. - M. Luchies, G. Groeseneken, and F. Kuper, "Grounded-gate nMOS transistor behavior under CDM ESD stress conditions", IEEE Trans. Electron Dev., vol. 44, 1997, pp. 1972-1980.
3. W. Wilkening, W. Stadler, J. Willemen, K. Esmark, H. Wolf H. Gieser, "Investigations on Charged Device Model for On-Chip protection in the ASDESE project", Proc. 7th ESD Forum'2001, Berlin, 2001, pp. 87 - 94.
4. H. Gieser and M. Haunschild, "Very fast transmission line pulsing of integrated structures and the charged device model", IEEE Trans. Compo Pack. Manuf. Tech. - Part c: vol. 21, 1998, pp. 278-285.
5. C. Russ, K. Verhaeghe, K. Bock, G. Groeseneken, and H. Maes, "Simulation study fro the CDM ESD behaviour of the grounded-gate NMOS", Microel. Reliab., vol. 36, 1996, pp. 1739-1742.
6. H. Wolt: H. Gieser, W. Wilkening, "Analyzing the switching behavior of ESD - protection transistors by very fast transmission line pulsing", Proc. EOSIESD Symp'99, 1999, Orlando (FL), USA, pp. 28-37.
7. J. Wu, P. Juliano, E. Rosenbaum, "Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions", Proc. EOSIESD Symp'2000, Anaheim, (CA), USA, 2000, pp. 287-295.
8. G. Meneghesso, M. Ciappa, P. Malberti, L. Sponton, G. Croce, C. Contiero, E. Zanoni, "Overstress and electrostatic discharge in CMOS and BCD integrated circuits", Microel. Reliab., vol. 40, 2000, pp. 1739-1746.
9. C. Fürböck, D. Pogany, M. Litzenberger, E. Gornik, N. Seliger, H. Gossner, T. Müller-Lynch, M. Stecher, W.Werner, "Interferometric temperature mapping during ESD stress and failure analysis of smart power technology ESD protection devices", J. Electrostatics, vol. 49, 2000, pp. 195-213.
10. C. Fürböck, K. Esmark, M. Litzenberger, D. Pogany, G. Groos, R. Zelsacher, M. Stecher, and E. Gornik, "Thermal and free carrier concentration mapping during ESD event in smart power ESD protection devices using an improved laser interferometric technique", Microel. Reliab., vol. 40, 2000, pp. 1365-1370.
11. K. Esmark, C. Fürböck, H. Gossner, G. Groos, M. Litzenberger, D. Pogany, R. Zelsacher, M. Stecher, and E. Gornik, "Simulation and experimental study of temperature distribution during ESD stress in smart-power technology ESD protection devices", Proc. IEEE Int. Reliab. Phys. Symp., (IRPS'2000), San Jose, California, April 10-13, 2000, pp. 304-309.
12. S. Bychikhin, M. Litzenberger, P. Kamvar, D. Pogany and E. Gornik G. Groos and M. Stecher, "Laser Interferometric Mapping of Smart Power ESD Protection Devices with Different Blocking Capabilities", in Proc. ESSDERC 2001, 2001, Nuremberg, Germany, pp. 231-234.
13. K. Esmark, W. Stadler, M. Wendel, H. Gossner, x. Guggenmos, W. Fichtner, "Advanced 2D/3D ESD device simulation - A powerful tool already used in a pre-Si phase", Proc. EOSIESD Symp. 2000, 2000, pp. 420-429.
14. M. Litzenberger, K. Esmark, D. Pogany, C. Fürböck, H. Gossner, E. Gornik, and W. Fichtner, "Study of triggering inhomogeneities in gg-nMOS ESD protection devices via thermal mapping using backside laser interferometry", Microel. Reliab., vol. 40, 2000, pp. 1359-1364.
15. M. Litzenberger, R. Pichler, S. Bychikhin, D. Pogany, K. Esmark, H. Gossner and E. Gornik, "Effect of pulse risetime on trigger homogeneity in single finger grounded gate nMOSFET electrostatic discharge protection devices", Microel. Reliab. vol. 41, 2001, pp. 1385-1390.
16. J. A. McCaulley, V. M. Donnelly, M. Vernon, and I. Taha, "Temperature dependence of the near-infrared refractive index of silicon, gallium arsenide, and indium phosphide", Phys. Rev. B., vol. 49, 1994, pp. 7408-7417.
17. R. A. Soref B. R. Bennett, "Electrooptical effects in silicon", IEEE J. Quant. Electron., vol. 23, 1987, pp. 123-129.
18. M. Goldstein, G. Sölkner, and E. Gornik, "Heterodyne interferometer for the detection of electric and thermal signals in integrated circuits through the substrate", Rev. Sci. Instr., vol. 64, 1993, pp. 3009-3013.
19. H. K. Heinrich, D. M. Bloom, and B. R. Hemenway, "Noninvasive sheet charge density probe for integrated silicon devices", Appl. Phys. Lett., vol. 48, 1986, pp. 1066-1068.
20. D. Pogany S. Bychikhin, C. Fürböck, M. Litzenberger, E. Gornik, G. Groos, K. Esmark, M. Stecher, "Quantitative internal thermal energy mapping of semiconductor devices under short current stress using backside laser interferometry", submitted to IEEE Trans. Electron Dev., March 2002.
21. T. J. Maloney, and N. Khurana, "Transmission line pulsing techniques for circuit modeling of ESD phenomena", Proc. EOSIESD Symp. 1985, 1985, pp. 49-54.
22. D. Pogany, N. Seliger, M. Litzenberger, H. Gossner, M. Stecher, T. Müller-Lynch, W. Werner and E. Gornik, "Damage analysis in smart power technology electrostatic discharge (ESD) protection devices", Microel. Reliab., vol. 39, 1999, pp. 1143-1148.
23. J. Colvin, "ESD failure analysis methodology", Microel. Reliab. vol. 38,1998, pp. 1705 - 1714.
24. K. G. McKay, "Avalanche breakdown in silicon", Phys. Rev., vol. 94, 1954, pp. 877-884.
25. S. Reggiani, M. Valdinoci, L. Colalongo, M. Rudan, G. Baccarani, A. D. Stricker, F. Illien, N. Felber, W. Fichtner, L. Zulino, "Electron and hole mobility in silicon at large operating temperatures - Part I: Bulk Mobility", IEEE Trans. Electron Dev., vol. 49, 2002, pp. 490-499.
26. D. Pogany, K. Esmark, M. Litzenberger, C. Fürböck, H. Gossner and E. Gornik, "Bulk and surface degradation mode in 0.35μm technology gg-nMOS ESD protection devices", Microel. Reliab, Vol. 40, 2000, pp.1467-1472.
27. D. C. Wunsch, and R. R. Bell, "Determination of threshold failure levels of semiconductor diodes and transistors due to pulse voltages", IEEE Trans. Nucl. Sci., vol. 15, 1968, pp. 244-259.
28. K. Esmark, "Device Simulation of ESD Protection Elements", Ph.D thesis, Hartung-Gorre Verlag, 2001.