Simulation study of HBM failure in an internal clock buffer and the design issues for efficient power pin protection strategy

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 1998, Pages 104-110

  Puvvada, Venugopal ^a   Duvvury, Charvaka ^a  

^a TEXAS INSTRUMENTS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC DISCHARGES; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; TIMING CIRCUITS;

ELECTROSTATIC DISCHARGE (ESD) PROTECTION;

ELECTRIC SHIELDING;

EID: 0032309922     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)