Computationally stable quasi-empirical compact model for the simulation of MOS breakdown in ESD-protection circuit design

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn , Issue , 1997, Pages 161-164

  Lim, Shiang Liang ^a   Zhang, Xin Yi ^a   Yu, Zhiping ^a   Beebe, Stephen ^a   Dutton, Robert W ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC DISCHARGES; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SEMICONDUCTOR JUNCTIONS; SUBSTRATES;

DRAIN SUBSTRATE SOURCE JUNCTIONS; ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT; PARASITIC BIPOLAR COLLECTOR CURRENT;

MOS DEVICES;

EID: 0030655005     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)