Study of a CMOS I/O protection circuit using circuit-level simulation

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 1997, Pages 333-338

  Li, T ^a   Suh, D ^a   Ramaswamy, S ^a   Bendix, P ^a   Rosenbaum, E ^a   Kapoor, A ^a   Kang, S M ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC DISCHARGES; ELECTROMAGNETIC SHIELDING; ELECTROSTATICS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MOS DEVICES; THYRISTORS;

ELECTROSTATIC DISCHARGES (ESD);

CMOS INTEGRATED CIRCUITS;

EID: 0030699010     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)