ESD-level circuit simulation - impact of gate RC-delay on HBM and CDM behavior

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2000, Pages 446-455

  Mergens, Markus P J ^a   Wilkening, Wolfgang ^a   Kiesewetter, Gerhard ^a   Mettler, Stephan ^a   Wolf, Heinrich ^a   Hieber, Juergen ^a   Fichtner, Wolfgang ^a  

^a ROBERT BOSCH GMBH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC DISCHARGES; ELECTRIC RESISTANCE; ELECTROSTATICS; MOS DEVICES;

ELECTROSTATIC DISCHARGES (ESD); METAL INTERCONNECTS; NONLINEAR GATE CAPACITANCES;

DELAY CIRCUITS;

EID: 0034538960     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)