Automatic layout based verification of electrostatic discharge paths

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn 2001-January, Issue , 2001, Pages 95-100

  Ngan, Paul ^a   Gramacy, Robert ^b   Wong, Ching Kwok ^c   Oliver, Dan ^a   Smedes, Theo ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Kestrel Solutions ^*  (United States)

Author keywords

BiCMOS integrated circuits; Circuit simulation; Data mining; Electrostatic discharge; Product design; Protection; Robustness; Silicon; Very large scale integration; Voltage

Indexed keywords

CIRCUIT SIMULATION; DATA MINING; ELECTRIC POTENTIAL; ELECTROSTATIC DISCHARGE; ELECTROSTATICS; PRODUCT DESIGN; ROBUSTNESS (CONTROL SYSTEMS); SILICON; VLSI CIRCUITS; VOLTAGE CONTROL;

AUTOMATIC LAYOUT; BI-CMOS; BICMOS INTEGRATED CIRCUITS; CONVENTIONAL DESIGN; ESD ROBUSTNESS; PARASITIC EXTRACTION; PROTECTION; VERIFICATION METHODOLOGY;

ELECTROSTATIC DEVICES;

EID: 84948987549     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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3. E. Dijkstra, A note on two problems in connexion with graphs: Numeriche Mathematics 1, 1959, p.269-271
4. Robert Gramacy, Shortest Paths and Network Flow Algorithms for Electrostatic Discharge Analysis, Senior Thesis, U.C. Santa Cruz, 2001
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