Influence of gate length on ESD-performance for deep sub micron CMOS technology

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 1999, Pages 95-104

  Bock, K ^a   Keppens, B ^a   De Heyn, V ^a   Groeseneken, G ^a   Ching, L Y ^a   Naem, A ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC DISCHARGES; ELECTROSTATICS; GATES (TRANSISTOR); MOS DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS;

ELECTROSTATIC DISCHARGES;

SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0033279350     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)