Bulk and surface degradation mode in 0.35μm technology gg-nMOS ESD protection devices

Microelectronics Reliability

Volumn 40, Issue 8-10, 2000, Pages 1467-1472

  Pogany, D ^a   Esmark, K ^b   Litzenberger, M ^a   Furbock C ^a   Gossner, H ^b   Gornik, E ^a  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0009966484     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(00)00157-8     Document Type: Article

References (8)

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2. Diaz C, Kopley TE and Marcoux PJ. Building-In ESD/EOS reliability for sub-halfmicron CMOS process. IEEE Trans. Electron Dev. 43 (1996) 991-999.
3. Richier C, Maene N, Mabboux G and Bellens R. Study of the ESD behavior of different clamp configurations in a 0.35μm CMOS technology. Microel. Reliab. 38 (1998) 1733-1739.
4. Amerasekera A, van den Abeelen W, van Roozendaal W, Hannemann M and Schofield P. ESD failure modes: characteristics, mechanisms and process influences. IEEE Trans. Electron Dev. 39 (1992) 430-435.
5. Aur S, Chatterjee A, and Polgreen T. Hot-electron reliability and ESD latent damage. IEEE Trans. Electron Dev. 35 (1988) 2189-2193.
6. Doyle BS, Krakauer DB, and Mistry KR. Examination of oxide damage during high-current stress of n-MOS transistors, IEEE Trans. Electron. Dev., 40 (1993) 980-985.
7. Verhaege K, Groeseneken G, Collinge J-P, and Maes HE. The ESD protection capability of SOI snapback nMOSFETs: Mechanisms and failure modes. Proc. EOS/ESD Symp. (1993) 215-219.
8. 2 layers. Appl. Phys. Lett. 73 (1998) 490-492.