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Volumn 24, Issue 2, 2000, Pages 85-96

TLP calibration, correlation, standards, and new techniques

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION DETECTORS; ELECTRIC ATTENUATORS; ELECTRIC DISCHARGES; ELECTRIC IMPEDANCE; ELECTRIC SWITCHES; ELECTROSTATICS; LEAKAGE CURRENTS; THROUGHPUT;

EID: 0034538752     PISSN: 07395159     EISSN: None     Source Type: Journal    
DOI: 10.1109/6104.930960     Document Type: Article
Times cited : (87)

References (26)
  • 1
    • 0024176692 scopus 로고
    • Electrical overstress testing of a 256K UVEPROM to rectangular and double exponential pulses
    • D. G. Pierce W. Shiley B. D. Mulcahy K. E. Wagner M. Wunder Electrical overstress testing of a 256K UVEPROM to rectangular and double exponential pulses Proc. EOS/ESD Symp. EOS-10 137 Proc. EOS/ESD Symp. 1988
    • (1988) , vol.EOS-10 , pp. 137
    • Pierce, D.G.1    Shiley, W.2    Mulcahy, B.D.3    Wagner, K.E.4    Wunder, M.5
  • 2
    • 0004638483 scopus 로고
    • A comparison of threshold damage processses in thick field oxide protection devices following square pulse and human body model injection
    • A. Bridgewood Y. Fu A comparison of threshold damage processses in thick field oxide protection devices following square pulse and human body model injection Proc. EOS/ESD Symp. EOS-10 129 Proc. EOS/ESD Symp. 1988
    • (1988) , vol.EOS-10 , pp. 129
    • Bridgewood, A.1    Fu, Y.2
  • 3
    • 0026220468 scopus 로고
    • Amerasekera L. v. Roozendaal J. Bruines F. Kuper Characterization and Modeling of 2nd Breakdown in NMOSTs for the Extraction of ESD-related Process and Design Parameters IEEE Trans. Electron Devices 38, 2161 2168 1991 16 2732 83744
    • (1991) , vol.38, , pp. 2161-2168
    • Amerasekera1    Roozendaal, L.v.2    Bruines, J.3    Kuper, F.4
  • 4
    • 0032320896 scopus 로고    scopus 로고
    • Non-Uniform Triggernig of ggNMOSt Investigated by Combined Emision Microscopy and Transmission Line Pulsing
    • A. Russ K. Bock M. Rasras I. DeWolf G. Groeseneken H. E. Maes Non-Uniform Triggernig of ggNMOSt Investigated by Combined Emision Microscopy and Transmission Line Pulsing Proc. EOS/ESD Symp. EOS-20 177 186 Proc. EOS/ESD Symp. 1998 5944 15886 737037
    • (1998) , vol.EOS-20 , pp. 177-186
    • Russ, A.1    Bock, K.2    Rasras, M.3    DeWolf, I.4    Groeseneken, G.5    Maes, H.E.6
  • 5
    • 0003571183 scopus 로고    scopus 로고
    • Basic ESD I/O Design
    • Wiley New York
    • S. Dabral T. J. Maloney Basic ESD I/O Design 1999 Wiley New York
    • (1999)
    • Dabral, S.1    Maloney, T.J.2
  • 6
    • 0000790344 scopus 로고
    • Improving the ESD failure threshold of silicided nMOS output transmission by ensuring uniform current flow
    • T. Polgreen A. Chatterjee Improving the ESD failure threshold of silicided nMOS output transmission by ensuring uniform current flow Proc. EOS/ESD Symp. EOS-11 167 174 Proc. EOS/ESD Symp. 1989
    • (1989) , vol.EOS-11 , pp. 167-174
    • Polgreen, T.1    Chatterjee, A.2
  • 7
    • 0003437663 scopus 로고
    • ESD in Silicon Integrated Circuits
    • Wiley New York
    • A. Amerasekera C. Duvvury ESD in Silicon Integrated Circuits 1995 Wiley New York
    • (1995)
    • Amerasekera, A.1    Duvvury, C.2
  • 8
    • 0028733647 scopus 로고
    • ESD protection elements during HBM stress tests̵further numerical and experimental results
    • C. Russ H. Gieser K. Verhaege ESD protection elements during HBM stress tests̵further numerical and experimental results Proc. EOS/ESD Symp. EOS-16 96 Proc. EOS/ESD Symp. 1994
    • (1994) , vol.EOS-16 , pp. 96
    • Russ, C.1    Gieser, H.2    Verhaege, K.3
  • 9
    • 0030274001 scopus 로고    scopus 로고
    • Rise time effects of HBM square pulses on the failure thresholds of ggNMOST
    • C. Musshoff H. Wolff H. Gieser P. Egger X. Gugenmos Rise time effects of HBM square pulses on the failure thresholds of ggNMOST Proc. 1996 ESREF Symp., Microelectron. Reliab. 36 1743 Proc. 1996 ESREF Symp., Microelectron. Reliab. 1996 7119 19180 888206
    • (1996) , vol.36 , pp. 1743
    • Musshoff, C.1    Wolff, H.2    Gieser, H.3    Egger, P.4    Gugenmos, X.5
  • 10
    • 0028735259 scopus 로고
    • Influence of tester parasitics on charged device model- failure thresholds
    • H. Gieser P. Egger Influence of tester parasitics on charged device model-failure thresholds Proc. EOS/ESD Symp. EOS-16 69 84 Proc. EOS/ESD Symp. 1994
    • (1994) , vol.EOS-16 , pp. 69-84
    • Gieser, H.1    Egger, P.2
  • 11
    • 85177111825 scopus 로고    scopus 로고
    • Application note #2
    • Tech. Rep., Barth Electronics NV, Boulder City
    • Application note #2 1999 Tech. Rep., Barth Electronics NV, Boulder City
    • (1999)
  • 12
    • 0028732943 scopus 로고
    • The impact of technology scaling on ESD robustness and protection circuit design
    • A. Amerasekera C. Duvvury The impact of technology scaling on ESD robustness and protection circuit design Proc. EOS/ESD Symp. EOS-16 237 245 Proc. EOS/ESD Symp. 1994
    • (1994) , vol.EOS-16 , pp. 237-245
    • Amerasekera, A.1    Duvvury, C.2
  • 13
    • 0031363103 scopus 로고    scopus 로고
    • On the Use of N Well Resistors for Uniform Triggering of ESD Protection Elements
    • G. Notermans On the Use of N Well Resistors for Uniform Triggering of ESD Protection Elements Proc. EOS/ESD Symp. EOS-19 221 Proc. EOS/ESD Symp. 1997 5018 13763 634246
    • (1997) , vol.EOS-19 , pp. 221
    • Notermans, G.1
  • 14
    • 0024169423 scopus 로고
    • Effects of interconnect process and snapback voltage on the ESD failure threshold of nMOS transistors
    • K. L. Chen Effects of interconnect process and snapback voltage on the ESD failure threshold of nMOS transistors Proc. EOS/ESD Symp. EOS-10 212 219 Proc. EOS/ESD Symp. 1988 16 449 8788
    • (1988) , vol.EOS-10 , pp. 212-219
    • Chen, K.L.1
  • 15
    • 0022219373 scopus 로고
    • ESD on CHMOS devices̵Equivalent circuits, physical models and failure mechanisms
    • N. Khurana T. Maloney W. Yeh ESD on CHMOS devices̵Equivalent circuits, physical models and failure mechanisms Proc. IEEE IRPS 212 Proc. IEEE IRPS 1985
    • (1985) , pp. 212
    • Khurana, N.1    Maloney, T.2    Yeh, W.3
  • 17
    • 0030398616 scopus 로고    scopus 로고
    • Very Fast Transmission line pulsing of integrated structures and the charged device model
    • H. Gieser M. Haunschild Very Fast Transmission line pulsing of integrated structures and the charged device model Proc. EOS/ESD Symp. EOS-18 85 94 Proc. EOS/ESD Symp. 1996 4126 18727 865129
    • (1996) , vol.EOS-18 , pp. 85-94
    • Gieser, H.1    Haunschild, M.2
  • 18
    • 0004638157 scopus 로고
    • An analysis of low voltage ESD damage in advanced CMOS processes
    • A. Amerasekera L. v. Roozendaal J. Abderhalden J. Bruines L. Sevat An analysis of low voltage ESD damage in advanced CMOS processes Proc. EOS/ESD Symp. EOS-12 143 150 Proc. EOS/ESD Symp. 1990
    • (1990) , vol.EOS-12 , pp. 143-150
    • Amerasekera, A.1    Roozendaal, L.v.2    Abderhalden, J.3    Bruines, J.4    Sevat, L.5
  • 19
    • 85177119458 scopus 로고
    • Enhanced $P+$ Substrate Tap Conductance in the Presence of NPN Snapback
    • T. J. Maloney Enhanced $P+$ Substrate Tap Conductance in the Presence of NPN Snapback Proc. EOS/ESD Symp. EOS-12 197 Proc. EOS/ESD Symp. 1990
    • (1990) , vol.EOS-12 , pp. 197
    • Maloney, T.J.1
  • 20
    • 0027794535 scopus 로고
    • Suppression of the soft ESD failures in a submicron CMOS process
    • F. Kuper J. M. Luchies J. Bruines Suppression of the soft ESD failures in a submicron CMOS process Proc. EOS/ESD Symp. EOS-15 117 122 Proc. EOS/ESD Symp. 1993 6074 16234 752873
    • (1993) , vol.EOS-15 , pp. 117-122
    • Kuper, F.1    Luchies, J.M.2    Bruines, J.3
  • 21
    • 0025607725 scopus 로고
    • Thermal breakdown of VLSI by ESD pulses
    • D. Lin Thermal breakdown of VLSI by ESD pulses Proc. 28th Annu. IRPS 281 287 Proc. 28th Annu. IRPS 1990 108 2374 66101
    • (1990) , pp. 281-287
    • Lin, D.1
  • 23
    • 85177132367 scopus 로고
    • CA., Stanford
    • S. G. Beebe Characterization, modeling, and design of ESD protection circuits 1994 Ph.D. thesis CA., Stanford
    • (1994)
    • Beebe, S.G.1
  • 24
    • 0002131374 scopus 로고    scopus 로고
    • Methodology for layout design and optimization of ESD protection transistors
    • S. Beebe Methodology for layout design and optimization of ESD protection transistors Proc. EOS/ESD Symp. EOS-18 255 Proc. EOS/ESD Symp. 1996 4126 18727 865152
    • (1996) , vol.EOS-18 , pp. 255
    • Beebe, S.1
  • 25
    • 0022212124 scopus 로고
    • Transmission line pulsing techniques for circuit modeling of ESD phenomena
    • T. Maloney N. Khurana Transmission line pulsing techniques for circuit modeling of ESD phenomena Proc. EOS/ESD Symp. EOS-7 49 54 Proc. EOS/ESD Symp. 1985
    • (1985) , vol.EOS-7 , pp. 49-54
    • Maloney, T.1    Khurana, N.2
  • 26
    • 0032659235 scopus 로고    scopus 로고
    • T. P. Chen R. Chan S. Fung K. F. Lo Reproducibility of transmission line measurement of bipolar $I\hbox{--}V$ characteristics of MOSFETs IEEE Trans Instrum Meas. 48 721 June 1999 19 16771 772206
    • (1999) , vol.48 , pp. 721
    • Chen, T.P.1    Chan, R.2    Fung, S.3    Lo, K.F.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.